Current Modeling in VITAL

Abstract

The recently approved VITAL [7] standard will permit many of the drawbacks presented by the use of VHDL at gate level to be overcome. It does not, however, address one of the basic problems at gate level: current modeling.

The main purpose of the present work is to propose a current modeling for VHDL gate-level descriptions which are VITAL compliant. This technique will be applied to different areas, such as low power design, BIST scheduling and fault simulation, for current fault modeling and for power estimation and average/peak current determination with a maximum variation of 10% with respect to the data obtained by SPICE LEVEL 3[1]. Logically, the new types, signals and subprograms used in current modeling do not verify the modeling rules of the recently approved VITAL standard, constituting a proposal for a possible extension in the future.

The order of contents of this paper will be as follows. In the next section the concepts necessary for transitory current modeling will be introduced. Then, an example of the application of this technique will be presented. The final section will present the conclusions of the article.