Exploitation of potential parallelism is obviously a major source of code optimization. This chapter therefore focusses on DSP-specific techniques, which aim at parallelization of generated vertical machine code. In the first part, we consider the area of memory address generation. Address generation for DSPs is strongly related to instruction-level parallelism, because taking into account the DSP-specific address generation hardware permits to maximize potential parallelism. In the second part of this chapter, we focus on exploitation of potential parallelism by code compaction. Code compaction identifies potential parallelism, accordingly arranges RTs in time, and generates executable machine code. We analyze the special demands on compaction techniques for DSPs, and we present a novel exact solution to the problem of local code compaction.
KeywordsDelay Line Control Step Schedule Length Address Generation Array Reference
Unable to display preview. Download preview PDF.