This chapter is concerned with mapping of algorithms to processor-specific RT patterns, which have been obtained by ISE. In this way, code generation algorithms can abstract from unnecessary hardware details. In turn, this enables the use of advanced and efficient code generation techniques. The main problem, however, is to cope with inhomogeneous architectures of DSPs, while achieving high code quality and retaining retargetability. We discuss how this problem is treated in related work, and we propose a partially integrated approach based on a fine-grained definition of code generation phases. This approach employs tree parsing as the key technique for a complete and retargetable code generation procedure for DSPs.
KeywordsCode Generation Transformation Rule Basic Block Tree Parser Grammar Rule
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