The previous Chapters were based on a relatively straight-forward understanding of how the Verilog simulator schedules and executes events. This Chapter develops a more detailed model of the simulator, including the processing of a number of the more subtle timing semantics of the language. Topics include the simulator scheduling algorithm, non-deterministic aspects of the language, and non-blocking assignments.
KeywordsEvaluation Event Behavioral Model Clock Period Advance Timing Simulation Cycle
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