Abstract
The ever-increasing density of ASICs, the whole-sale switch to surfacemount technology, and the growing interest in multi-chip modules (MCM), have resulted in testable designs becoming a greater priority. Thus far, designers have considered testability as an issue which comes into play at the very end of the design cycle. However, in the ASIC design flow based on synthesis, it is essential that designers develop a test strategy and address testability issues concurrently with other activities in the design cycle. In this chapter, Test Synthesis and Automatic Test Pattern Generation (ATPG) using the Synopsys Test Compiler (referred to as TC, for short), are discussed.
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Recommended further reading
Test Compiler Reference Manual v3.2a chapter 5,7,11,12
Test Compiler Streamlined Methodology Application Note
Fall 1994 Synopsys Newsletter Impact Support Center Q&A
Winter 1994 Synopsys Newsletter Impact Support Center Q&A
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© 1995 Springer Science+Business Media New York
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Kurup, P., Abbasi, T. (1995). Design for Testability. In: Logic Synthesis Using Synopsys®. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2370-0_6
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DOI: https://doi.org/10.1007/978-1-4757-2370-0_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2372-4
Online ISBN: 978-1-4757-2370-0
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