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Coding in HDL for Synthesis

  • Pran Kurup
  • Taher Abbasi

Abstract

This chapter provides several examples of HDL coding for synthesis. Coding for Finite state machines has also been discussed in detail with several examples. Concepts such as priority encoding, parallel case and full-case directives have been discussed along with simple examples to infer counters, shift registers, decoders and ALU. Tips for FSM coding and general guidelines for HDL coding for synthesis have been provided.

Keywords

State Machine Case Statement Finite State Machine Flip Flop Logic Synthesis 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Recommended further reading

  1. 1.
    VHDL Compiler Reference Manual v3.2a,chapter 4,6,8,11Google Scholar
  2. 2.
    HDL Compiler for Verilog Reference Manual v3.2a,chapter 5,6,7,9Google Scholar
  3. 3.
    HDL Coding Styles: Sequential Devices Application NoteGoogle Scholar
  4. 4.
    Fall 1994 Synopsys Newsletter Impact Support Center QAGoogle Scholar
  5. 5.
    Winter 1994 Synopsys Newsletter Impact Support Center QAGoogle Scholar

Copyright information

© Springer Science+Business Media New York 1995

Authors and Affiliations

  • Pran Kurup
    • 1
  • Taher Abbasi
    • 2
  1. 1.Cirrus Logic, Inc.USA
  2. 2.Synopsys, Inc.USA

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