This chapter provides several examples of HDL coding for synthesis. Coding for Finite state machines has also been discussed in detail with several examples. Concepts such as priority encoding, parallel case and full-case directives have been discussed along with simple examples to infer counters, shift registers, decoders and ALU. Tips for FSM coding and general guidelines for HDL coding for synthesis have been provided.
KeywordsState Machine Case Statement Finite State Machine Flip Flop Logic Synthesis
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Recommended further reading
- 1.VHDL Compiler Reference Manual v3.2a,chapter 4,6,8,11Google Scholar
- 2.HDL Compiler for Verilog Reference Manual v3.2a,chapter 5,6,7,9Google Scholar
- 3.HDL Coding Styles: Sequential Devices Application NoteGoogle Scholar
- 4.Fall 1994 Synopsys Newsletter Impact Support Center QAGoogle Scholar
- 5.Winter 1994 Synopsys Newsletter Impact Support Center QAGoogle Scholar