Three Large Examples
MiniSim is a description of a very simplified gate level simulator. Only three primitives have been included: a nand gate, a D positive edge-triggered flip flop, and a wire that handles the full strength algebra that is used in Verilog. All primitive timing is unit delay, and a record is kept of the stimulus pattern number and simulation time within each pattern. Each primitive is limited to two inputs and one output that has a maximum fanout of two.
KeywordsNand Gate Cache Instruction Instruction Fetch Primitive Timing Side Instruction
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