The heart of a digital system is its clock, which is the control signal that synchronizes the flow of data among functional elements. To achieve maximum system performance, it is necessary to limit the clock skew, i.e., the maximum difference in arrival times of the clock signal at synchronizing elements (sequential registers, or clock sinks) of the design. This has been idealized in the recent literature as the “zero-skew clock routing problem”, which seeks a routing tree that delivers the synchronizing clock pulse from its source to all clock sinks simultaneously. At the same time, the cost of the clock routing tree must be minimized in light of system power requirements, signal integrity, and area utilization. This chapter views clock tree construction to minimize skew and tree cost as a combination of two processes — topology generation and geometric embedding — and presents methods which accomplish each of these processes using either linear delay or Elmore delay to guide the construction. Our focus is on the sequence of recent works by Jackson et al. , Kahng et al. , Tsay , Boese et al.  Chao et al. [44, 45], Edahiro [82, 84], Zhu and Dai , and Kahng and Tsao  which lead to the present state of single-layer, exact zero-skew clock tree constructions.
KeywordsDelay Model Balance Point Connection Topology Linear Delay Sink Location
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