A low-voltage high-frequency CMOS fully-balanced filtering technique is presented. The low internal voltage characteristic of current-mode circuits allows the operation at power supply voltages as low as 3-V with high dynamic range. The integrator time-constant is determined by a MOSFET small-signal transconductance and an additional non-critical MOSFET gate capacitance. For ladder filters derived from doubly-terminated LC prototypes, HSPICE simulations predict a -3-dB bandwidth of 125 MHz for a three-pole lowpass filter. Power dissipation is 6 mW/pole with a 3-V power supply.
KeywordsNegative Input Small Signal Model Output Conductance HSPICE Simulation Chebyshev Filter
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