New RF Devices Based on High Precision CMOS Time-to-Digital and Digital-to-Time Converters
The implementation of FM/PM demodulation based on direct cycle time measurement is feasible and attractive way to integrate FM receivers. Cycle time measurement is based on CMOS delay lines used as Time-to-Digital Converters (TDC). An experimental chip shows performance, size and current consumption comparable with the traditional quadrature phase shifter based IF/FM demodulator circuits and the level of achievable integration to be much better.
The use of CMOS delay lines as Digital-to-Time Converters (DTC) together with interpolation principle makes it possible control time intervals down to a few pico seconds. The interpolating phase locked loop frequency synthesizer, (IDPLL), is shown capable to adjust the phase of up to 2 GHz RF signals down to a small fraction of cycle time, thus facilitating small frequency steps, fast switching and settling together with low noise, and finally a digitally controllable, simple means for phase and frequency modulation.
With the current state-of-the art 63/64 tap CMOS delay lines with 40 ns range show an accuracy better than ± 0.5 ns which, in turn, results in an FM demodulator and an IDPLL synthesizer performance meeting radio telephony requirements.
KeywordsDelay Line Loop Filter Frequency Synthesizer Delay Element Phase Comparator
Unable to display preview. Download preview PDF.
- /1/.Design of VLSI circuits for Telecommunications and Signal Processing, Prentice-Hall 1993, Edited by J. Franca and Y. Tsividis (in printing), Chapter 5 “IC solutions for Mobile Telephones” by J. Rapeli.Google Scholar
- /2/.Boutin, N: An arctangent type wideband FM/PM modulator with improved performance, IEEE Tr. on Consumer Electronics Vol 38 (1), Feb 1992Google Scholar
- /3/.Plessey Semiconductors (product literature), SP2007 500 MHz Direct Frequency Synthesizer (Nov. 89)Google Scholar
- /4/.Qualcomm Inc. (product literature), Q2334 Dual Direct Digital Synthesizer (Jan. 1989)Google Scholar
- /5/.US. Pat. 5,093,632 (Motorola, Inc.)Google Scholar
- /6/.US. Pat. 5,079,520 (Nokia Mobile Phones Ltd)Google Scholar
- /7/.Rahkonen T, Kostamovaara J: The use of stabilized CMOS delay lines in the digitization of short time intervals, Proc. ISCAS 91Google Scholar
- /8/.Rahkonen T, Kostamovaara J: The use of stabilized CMOS delay lines for the digitization of short time intervals, Manuscript accepted for publication in IEEE JSSCGoogle Scholar
- /9/.Rahkonen T, Kostamovaara J: A programmable CMOS delay generator with sub-ns resolution and built-in range stabilization, Proposed paper for ESSCIRC’93Google Scholar