Advertisement

Combinational Logic and Optimization

  • Douglas E. Ott
  • Thomas J. Wilderotter
Chapter

Abstract

This chapter discusses the synthesis of purely combinational circuits, and how the logic optimization capabilities of synthesis tools can be used to control gate count and path delays through the logic. In the examples, the interaction of the ASIC library with the optimization tools will be illustrated along with the effect of the library’s rules for loading and wire delays.

Keywords

Full Adder Combinational Logic Combinational Circuit Logic Minimization Synthesis Tool 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Copyright information

© Springer Science+Business Media New York 1994

Authors and Affiliations

  • Douglas E. Ott
    • 1
  • Thomas J. Wilderotter
    • 1
  1. 1.ITT AvionicsUSA

Personalised recommendations