Logic synthesis tools and hardware description languages are beginning to create a revolution in the way ASIC systems are designed. This major change is primarily a result of rapidly moving developments in semiconductor technology and design processes as well as the general need for improving both design quality and productivity. This introductory chapter will discuss, from a management viewpoint, what synthesis is and why it has been developed, the advantages of using VHDL based synthesis, and some of the facts, the hype, and the misconceptions that may be confusing to someone trying to assess the process. The rest of the book is then devoted to the issues of how to put VHDL synthesis successfully into your current design practice.
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