Analog Cell-Level Synthesis using a Novel Problem Formulation
A novel formulation of the cell-level analog circuit synthesis problem is presented in this chapter. This novel formulation is characterized by the use of encapsulated device evaluators, the use of do-free biasing, and the use of Asymptotic Waveform Estimation to compute low order pole/zero models of small signal transfer functions. This synergistic combination of elements makes it possible to design high performance analog circuits using high accuracy device models while requiring greatly reduced expert designer input in the form of equations describing circuit behavior.
KeywordsPerformance Prediction Analog Circuit Phase Margin Device Model Node Voltage
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