In the course of this dissertation, a number of design exercises featuring industrial complexity have been done with CATHEDRAL-II. In this chapter, an evaluation of the most important aspects of CATHEDRAL-II is presented. In addition, the consequences of high-level design decisions on the overall chip area will be illustrated with elaborated design examples. CATHEDRAL-II combines a number of optimising transformations. The relative importance of these optimisations will be evaluated. We will demonstrate that some optimisations may have unexpected side-effects on the performance or on the chip area. The importance of user interaction will be stressed. In order to draw relevant conclusions, a detailed chip layout has been generated for each design alternative, including pads and hardware for testability. The overhead of testability in terms of chip area will be evaluated.
KeywordsPulse Shaper Clock Cycle Delay Line Data Path Chip Area
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