Abstract
Boundary-Scan, formally known1 as IEEE/ANSI Standard 1149.1–1990 [IEEE90, Maun90], is a collection of design rules applied principally at the Integrated Circuit (IC) level that allow software to alleviate the growing cost of designing and producing digital systems. The primary benefit of the standard is its ability to transform extremely difficult printed circuit board testing problems that could only be attacked with Ad-Hoc testing methods [Wi1l83] into well-structured problems that software can easily and swiftly deal with.
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Informally, the Standard is often referred to as the “JTAG” proposal, due to its history of development. JTAG was the Joint Test Action Group made up of companies primarily in Europe and North America. This group created the foundation for the IEEE work.
In this book, the term “Standard” shall refer to 1149.1–1990. Supplements will be specifically mentioned by name, such as “P1149.1A”.
There were many examples of proprietary systems in existence well before this time, typically at the larger, vertically-integrated electronics manufacturers.
In the early days of simulation (late 1960s) simple gate level models or systems of Boolean logic equations were used to describe circuits. Now there is a range of technology spanning transistor-level models to high-level behavioral models.
“Faults” are an abstraction. The most popular fault model is the Single Stuck-at fault model. Considering multiple Stuck-at faults can quickly become intractable. Thus, “all faults” means all faults that are practical to consider.
Automatic Test Generation software has had marginal success in supplanting humans in this task. In cases where strict design rules are obeyed, automation can be achieved. For the bulk of electronics manufacturers, this has not been practical.
Stimulating embedded nodes requires the ability to overdrive the states that upstream ICs may be driving. This “backdrive” capability requires tester drivers that can source/sink in excess of 700 milliamperes of current (at speed) for many of today’s logic families.
A “via” is a cylindrical conductor that makes a physical connection between segments of a node on different layers of a printed circuit board. Most vias traverse the entire thickness of the board and are thus visible to In-Circuit nails. These are referred to as “natural” test points [Bu1187].
In the literature, the term “System Logic” has a number of synonyms. Some are: core logic, internal logic, and mission logic.
As in the Standard itself, signals that are asserted or active in the low state will have an asterisk suffix. All others are asserted in the high state.
Making TRST* optional allows the tradeoff of having an asynchronous reset for the TAP versus the cost of adding a fifth pin.
This requirement implies the use of internal pullups on these pins, which consume current. There are two negatives to this that sometimes tempt designers to ignore the float-high rule: first, in ultra-low power systems (for example, battery-powered), the extra power drain is a concern. Second, the quiescent current consumption in CMOS ICs (IDDQ) is significantly higher, which frustrates IDDQ testing [Hawk85], an example of two testing methodologies in conflict. component: the Bypass Register and the Boundary Register. Several others are described by the Standard, such as an Identification Register, but are optional. Finally, rules are given for adding user-defined data registers.
Discussion of Instruction Register codes will be found in following sections.
Upon entering TEST-LOGIC-RESET by means of clocking TCK, it is necessary to return TCK to 0 (a falling edge) to completely reset certain portions of the 1149.1 logic that are sensitive to falling edges of TCK. TRST* on the other hand completely resets all 1149.1 circuitry immediately. sequence is initiated for the selected test data register. If TMS is held high, the controller moves on to the SELECT-IR-SCAN state. SELECT-IR-SCAN This is a temporary controller state. Here, a decision is made whether to enter the Instruction Register (IR) column, or to reset the TAP Controller by returning to the TEST-LOGIC-RESET state. If TMS is held low when the controller is in this state, then the controller moves into the CAPTURE-IR state and a scan sequence is initiated for the Instruction Register. If TMS is held high, the controller returns to the TEST-LOGICRESET state. In this controller state, the shift-register15 contained in the Instruction Register parallel loads a pattern of fixed logic values on the rising edge of TCK. The two least significant bits16 are assigned the values “01”. Any higher-order bits of the Instruction Register, if they exist, may receive fixed bit values or design specific values. This bit pattern is not necessarily an instruction; it has significance as a test pattern for the integrity of the 1149.1 circuitry as will be seen in Chapters 3 and 5.
Registers are constructed with dual ranks, a shiftable part and a hold part to prevent rippling, due to shifting, from being visible to downstream logic. When we say a register is shifted, we mean the shift portion of it is connected between TDI and TDO.
Throughout this book, any pattern of bits will be displayed with the most significant bit on the left, through to the least significant on the right. The least significant bit would be the first bit shifted into TDI or out from TDO.
The meaning of “write operation” will become clearer in the description of the Boundary Register. The meaning of “write operation” will become clearer in the description of the Boundary Register.
However, if an instruction is marked private then the size and purpose of a target register might or might not be documented.
On close examination of Figure 1–8 you will notice that it cannot monitor the output pin while the driver is enabled. While a compliant design, it is considered flawed by this lack of visibility. Supplement A [IEEE92a] shows an improved design that does allow driver monitoring.
Exceptions could occur when some of the ICs have a an optional TRST* pin. We assume all ICs are synchronized to TEST-LOGIC-RESET and that no assertions are made to TRST*.
If a pin-permission mode has been entered, it may be necessary to perform a reset upon both the Boundary-Scan logic and the System Logic before the System Logic will operate normally. In some cases, the surest, safest way of achieving this is by cycling the power.
The Standard also states that all unused instruction codes not declared to be private must also decode to BYPASS.
Also, any reversible cell set to listen to a bidirectional I/O pin will capture its state.
These tests are not the same as those applied by an IC tester in parallel to the component I/O pins. The tests must be prepared for the System Logic I/O signals. For each bus or bidirectional pin, there may be several System Logic I/O signals.
This may be only partially true if rule 10.6.1c(ii) of the Standard is followed in the design of any of the Boundary Register cells. This rule allows the INTEST (also RUNBIST) function to directly disable output drivers. Disabled outputs may seem safe, but downstream board logic might be confused by high-impedance values on inputs.
This IC is one of several in a family (called the SCOPE octals) that all implement the same extensions. SCOPE is a trademark of Texas Instruments.
The price for eliminating these multiplexers might be the inability to implement the optional INTEST instruction.
Vishwani Agrawal of AT&T originated this phrase. It beautifully states that many of our testing problems can be solved by placing some responsibility for the product’s economic success on the design team. This requires management support.
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© 1992 Springer Science+Business Media New York
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Parker, K.P. (1992). Boundary-Scan Basics and Vocabulary. In: The Boundary-Scan Handbook. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2142-3_1
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DOI: https://doi.org/10.1007/978-1-4757-2142-3_1
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