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Device Simulation for Silicon ULSI

  • M. R. Pinto
  • W. M. CoughranJr.
  • C. S. Rafferty
  • R. K. Smith
  • E. Sangiorgi
Chapter
Part of the The Springer International Series in Engineering and Computer Science book series (SECS, volume 113)

Abstract

Device simulation has played a significant role in the evolution of IC technology, providing critical insight into device scaling, leading to the advent of VLSI. Simulators continue to be applied in the analysis of new device concepts and have become an essential component of the technology design process [1]. As scaling continues into the ULSI realm (≤0.25μm), device simulation faces new challenges, necessitating improvements to both physical and numerical capabilities. It is the purpose of this paper to outline these challenges and to suggest algorithmic steps toward the development of a physically-based device simulation tool, predictive into the deep-submicron regime.

Keywords

Monte Carlo Velocity Overshoot Device Scaling Leakage Simulation Prismatic Grid 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    R. W. Dutton and M. R. Pinto, Proc. IEEE, p. 1730, 1986.Google Scholar
  2. [2]
    M. R. Pinto, et. al., IEDM Tech. Dig., p. 288, 1984.Google Scholar
  3. [3]
    G. A. Sai-Halasz, et al., IEEE Electron Dev. Lett., p. 464, 1988.Google Scholar
  4. [4]
    K. Singhal, et. al., AT&T Tech. J., p. 77, 1989.Google Scholar
  5. [5]
    W. van Roosbroeck, Bell Syst. Tech. J., p. 560, 1950.Google Scholar
  6. [6]
    K. BLatekjaer, IEEE Trans. Electron Dev., p. 38, 1970.Google Scholar
  7. [7]
    C. Jacoboni and L. Reggiani, Rev. Mod. Phys., p. 645, 1983.Google Scholar
  8. [8]
    F. Venturi, et. al., IEEE Trans. CAD of ICs, p. 360, 1989.Google Scholar
  9. [9]
    R. R. Troutman, Latchup in CMOS Technology, Kluwer, 1986.Google Scholar
  10. [10]
    W. M. Coughran, Jr., et al., IEEE Trans. CAD of ICs, p. 307, 1988.Google Scholar
  11. [11]
    W. M. Coughran, Jr., et al., J. Comp, and Appl. Math., p. 47, 1989.Google Scholar
  12. [12]
    M. R. Pinto and R. W. Dutton, IEEE Electron Dev. Lett., p. 100, 1985.Google Scholar
  13. [13]
    R. E. Bank, et al., IEEE Trans. Electron Dev., p. 1992, 1985.Google Scholar
  14. [14]
    R. E. Bank and A. Weiser, Math. Comp., p. 283, 1985.Google Scholar
  15. [15]
    R. Stratton, Phys. Rev., p. 2002, 1962.Google Scholar
  16. [16]
    G. Baccarani and M. R. Wordeman, Solid-St. Electron., p. 407, 1985.Google Scholar
  17. [17]
    E. Sangiorgi, et al., IEEE Electron Dev. Lett., p. 13, 1988.Google Scholar
  18. [18]
    C. S. Rafferty, Ph.D. thesis, Stanford University, 1989.Google Scholar
  19. [19]
    R. E. Bank, et al., in Process and Device Modeling, North-Holland, 1986.Google Scholar
  20. [20]
    R. E. Bank, et al., Computer Phys. Comm., p. 201, 1989.Google Scholar
  21. [21]
    R. E. Bank, et al., BIT, p. 938, 1989.Google Scholar
  22. [22]
    R. E. Bank, et. al., in Mathematical Modelling and Simulation of Electrical Circuits and Semiconductor Devices, Birkhäuser, p. 125, 1990.Google Scholar
  23. [23]
    W. M. Coughran, Jr. and E. H. Grosse, in Proceedings of the 1990Google Scholar

Copyright information

© Springer Science+Business Media New York 1991

Authors and Affiliations

  • M. R. Pinto
    • 1
  • W. M. CoughranJr.
  • C. S. Rafferty
    • 1
  • R. K. Smith
    • 1
  • E. Sangiorgi
    • 2
  1. 1.AT&T Bell LaboratoriesMurray HillUSA
  2. 2.Department of PhysicsUniversity of UdineItaly

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