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Abstract

In the early days of integrated circuits, analog circuits were built primarily in bipolar technologies. Much of the design methodology for analog integrated circuits evolved from the bipolar technologies with vertical npn transistors and lateral pnp transistors. While bipolar analog integrated circuits continued to develop, NMOS technologies were becoming popular in digital integrated circuits for their high packing density. For analog applications, despite the inherent drawbacks of NMOS circuits such as low gain, difficult level shifting, and large offset voltages, many clever circuit design techniques were invented to overcome the shortcomings, and take full advantage of NMOS technologies [8.18.4].

Keywords

Operational Amplifier Analog Circuit Bipolar Transistor Voltage Gain Current Mirror 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 8.1]
    J.L. McCreary and P.R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques-Part I,” IEEE J. Solid-State Circuits, vol. SC-10, pp. 371–378, Dec. 1975.Google Scholar
  2. 8.2]
    I.A. Young, DA. Hodges, and P.R. Gray, “Analog NMOS sampled-data recursive filter,” in ISSCC Dig. Tech. Papers, pp. 156–157, Philadelphia, PA, Feb. 1977.Google Scholar
  3. 8.3]
    Y.P Tsividis and P.R. Gray, “An integrated NMOS operational amplifier with internal compensation,” IEEE J. Solid-State Circuits, vol. SC-11, pp/748–753, Dec. 1976.Google Scholar
  4. 8.4]
    D. Senderowicz, S.F. Dreyer, J.H. Huggins, C.F Rahim, and C.A. Laber, “A family of differential NMOS analog circuits for a PCM CODEC filter chip,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1014–1023, Dec. 1982.Google Scholar
  5. 8.5]
    B.J. White, G.M. Jacobs, and G.F. Landsburg, “A monolithic dual tone multifrequency receiver,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 991–997, Dec. 1979.Google Scholar
  6. 8.6]
    Y.A. Hague, R Gregorian, R.W. Blasco, RA. Mao, and W. E. Nicholson, Jr., “A two chip PCM voice CODEC with filters,” IEEE J. Solid-State Circuits, vol. SC-14, pp. 961–969, Dec. 1979.Google Scholar
  7. 8.7]
    H.-S. Lee, D.A. Hodges, and P.R. Gray, “A self-calibrating 15 bit CMOS A/D converter,” IEEE J. Solid-State Circuits, vol SC-19, pp. 813–819, Dec. 1984.Google Scholar
  8. 8.8]
    B. K. Ahuja and W.M. Baxter, “A programmable dual channel interface processor,” in ISSCC Dig. Tech. Papers, pp. 232–233, San Fransisco, CA, Feb. 1984.Google Scholar
  9. 8.9]
    M. Tadauchi, N. Hamada, K. Sato, K. Yasunari, Y. Nagayama, K. Nagai, N. Suemori, and T. Kubo, “A CMOS facsimile video signal processor,” IEEE J. Solid-State Circuits, vol. SC-20, pp. 1179–1184, Dec, 1985.Google Scholar
  10. 8.10]
    K.K. O, 11.-S. Lee, R. Reif, and W. Frank, “A 2 µm BiCMOS process utilizing selective epitaxy,” IEEE Electron Device Letters, vol. 9, pp. 567–569, Nov. 1988.CrossRefGoogle Scholar
  11. 8.11]
    T. Yamaguchi, Y. Wakui, K. Inayoshi, C. Tsuchiya, and M. Tokuriki, “20V BiCMOS technology with polysilicon emitter structure,” in Extended Abstracts, Electrochem. Soc. Meeting (Spring), pp. 419–420, Philadelphia, PA, May, 1987.Google Scholar
  12. 8.12]
    T. Ikeda, A. Watanabe, Y. Nishio, I. Masuda, N. Tamba, M. Odaka, and K. Ogiue, “High-speed BiCMOS technology with a buried twin well structure, IEEE Trans. Electron Devices, vol. ED-34, pp. 1304–1310, June, 1987.Google Scholar
  13. 8.13]
    T.L. Tewksbury, H.-S. Lee, and G.A. Miller, ‘The effects of oxide traps on the large-signal transient response of MOS circuits,“ to appear in IEEE J. Solid-State Circuits.Google Scholar
  14. 8.14]
    J.L. McCreary, “Matching properties, and voltage and temperature dependence of MOS capacitors,” IEEE J. Solid-State Circuits, vol. SC-16, pp. 608–616, Dec. 1981.Google Scholar
  15. 8.15]
    R. Castello and P.R. Gray, “Performance limitations in switched-capacitor filters,” IEEE Trans. Circuits Syst. vol. CAS-32, pp. 865–876, Sept. 1985.Google Scholar
  16. 8.16]
    P.R. Gray and R.G Meyer, Analysis and Design of Analog Integrated Circuits, 2nd ed. New York, Wiley, 1984.Google Scholar
  17. 8.17]
    R.S. Muller and T.I. Kamins, Device Electronics for Integrated Circuits, 2nd ed. New York, Wiley, 1986.Google Scholar
  18. 8.18]
    R. Gregorian and G.C. Ternes, Analog MOS Integrated Circuits for Signal Processing, New York, Wiley, 1986.Google Scholar
  19. 8.19]
    P.E. Gray and C.L. Searle, Electronic Principles, Physics, Models, and Circuits, New York, Wiley, 1969.Google Scholar
  20. 8.20]
    J.K. Roberge, Operational Amplifiers: Theory and Practice, New York, Wiley, 1975.Google Scholar
  21. 8.21]
    T.C. Choi, R.T. Kaneshiro, R.W. Brodersen, P.R. Gray, W.B. Jett, and M. Wilcox, “High-frequency CMOS switched-capacitor filters for communications application,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 652–664, Dec. 1983.Google Scholar
  22. 8.22]
    P.W. Li, M.J. Chin, P.R. Gray, and R. Castello, “A ratio-independent algorithmic analog-to-digital conversion technique,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 828–836, Dec. 1984.Google Scholar
  23. 8.23]
    B.S. Song and M.F. Tompsett, “A 12b 1 MHz capacitor error averaging pipelined A/D converter,” in ISSCC Dig. Tech. Papers, pp. 226–227, San Fransisco, CA, Feb. 1988.Google Scholar
  24. 8.24]
    B. Gilbert, ‘Translinear Circuits: a proposed classification,“ Electronic Letters, vol. 11, Jan. 1975.Google Scholar
  25. 8.25]
    M. Soyuer, High-frequency monolithic phase-locked loops, Ph. D. Dissertation, University of California, Feb. 1988.Google Scholar
  26. 8.26]
    K.M. Ware, H.-S. Lee, and C.G. Sodini, “A 200 MHz CMOS PLL,” in ISSCC Digest Tech. Papers, New York, N.Y., Feb. 1989.Google Scholar
  27. 8.27]
    M. Kubo, I. Masuda, K. Miyata, and K. Ogiue, “Perspective on BiCMOS VLSI’s,” IEEE J. Solid State Circuits, vol. SC-23, pp 5–11, Feb. 1988.Google Scholar
  28. 8.28]
    N. Tamba, S. Miyaoka, M. Odaka, K. Ogiue, K. Yamada, T. Ikeda, M. Hirao, H. Higuchi, H. Uchida, “An 8ns 256K BiCMOS SRAM,” in ISSCC Dig. Tech. Papers, pp. 184–185, San Fransisco, CA, Feb. 1988.Google Scholar
  29. 8.29]
    H. V. Tran, D.B. Scott, P.K. Fung, R.H. Havemann, R.E. Eklund, T.E. Ham, R.A. Haken, A. Shah, “An 8m battery back-up submicron BiCMOS 256K ECL SRAM,” in ISSCC Dig. Tech. Papers, pp. 188–189, San Fransisco, CA, Feb. 1988.Google Scholar

Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • H.-S. Lee
    • 1
  1. 1.Massachusetts Institute of TechnologyUSA

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