Abstract
Over the past few years, memory performance has been the primary demonstration vehicle for BiCMOS technologies. Intrinsic gate delay, power dissipation and area have been regarded as the theoretical indications for technology performance and density. In a similar manner memory access time, memory power dissipation and memory size have been regarded as the practical indications of technology performance and density. Against this empirical yard stick BiCMOS technology has been found to produce memories with MOS-like power and density but with speeds and I/O interfaces which one normally attributes to bipolar memories.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
T.S.Yang et al.,“ A 4-ns 4K x 1-bit Two-Port B iCMOS RAM,” JS SC Vol.23, pp. 1030–1040, Oct. 1988
B. A. Chappell et al., “ Fast CMOS ECL Receivers With 100mV Worst-Case Sensitivity,” IEEE J. Solid State Circuits, vol. 23, pp. 59–67, Feb. 1988.
M. Yoshimoto et al.,“ A 64Kb Full CMOS RAM with Divided Word Line structure”, Digest of Tech. Papers. pg. 58, ISSCC, Feb. 1983 N.Y
R. Hon et al.,“An experimental 35ns 1Mb BiCMOS DRAM’s”, Digest Of Tech. Papers. p. 280, ISSCC. Feb. 1987, N.Y
S. Watanabe et al., “BiCMOS Circuit Technology for High Speed DRAM’s.” 1987 Symposium on VLSI Circuits, pp. 79–80, Aug. 1987, Karuizawa, Japan
E. Hudson and S. Smith, “An ECL compatible 4K CMOS RAM,” in ISSCC Dig. Tech. Papers, vol. XXV, Feb. 1982, pp. 248–249.
Y.Ohmori et al., “An ECL compatible 64Kb FIFOS/CMOS static RAM,” in Extended Abst. 17th Conf. Solid State Devices and Materials (Tokyo), 1985, pp. 53–56.
T. I. Chappell et al., “ A 6.2ns 64Kb CMOS RAM with ECL Interfaces,” Symp. on VLSI Circuits Dig of Tech. Papers, Aug. 1988, pp. 19–20.
S. Miyaoka et al., “ A 7ns/350mW 64K ECL Compatible RAM,” in ISSCC Dig. Tech. Papers, vol. XXX, Feb. 1987, pp. 132–133.
K. Ogiue et al., “ A 13ns/500mW 64Kb ECL RAM,” in ISSCC Dig. Tech. Papers, vol. XXIX, Feb. 1986, pp. 212–213.
R. A. Kertis et al., “A 12ns 256K BiCMOS SRAM” in ISSCC Dig. Tech. Papers, vol. XXXI, Feb. 1988, pp. 186–187.
H. V. Tran et al., “ An 8ns Battery Back-up Submicron BiCMOS 256K ECL SRAM,” in ISSCC Dig. Tech. Papers, vol. XXXI, Feb. 1988, pp. 188–189.
H. V. Tran et al., “ A Novel BiCMOS TTL Input Buffer; A Merging of Analog and Digital Circuit Design Techniques,” Symp. on VLSI Circuits Dig of Tech. Papers, Aug. 1988, pp. 65–66.
K. Sasaki et al., “A 15 ns 1Mb CMOS SRAM,” in ISSCC Dig. Tech. Papers, vol. XXXI, Feb. 1988, pp. 174–175.
N. Homma et al., “A 3.5-ns, 2-W, 20-mm2, 16-kbit ECL Bipolar RAM,” IEEE J. Solid State Circuits, vol. 21, pp. 675–680. Oct. 1986.
M. Nakashiba et al., “A Subnanosecond BiCMOS Gate-Array Family,” Proceedings of IEEE 1986 CICC, pp. 63–66, May 1986
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1990 Springer Science+Business Media New York
About this chapter
Cite this chapter
Tran, H.V., Fung, P.K., Scott, D.B., Shah, A.H. (1990). BiCMOS Standard Memories. In: Alvarez, A.R. (eds) BiCMOS Technology and Applications. The Springer International Series in Engineering and Computer Science, vol 76. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2029-7_6
Download citation
DOI: https://doi.org/10.1007/978-1-4757-2029-7_6
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2031-0
Online ISBN: 978-1-4757-2029-7
eBook Packages: Springer Book Archive