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Abstract

The increasing acceptance of BiCMOS as a viable technology has brought to the forefront new challenges for the device physicist/designer. Ultimately, the device designer wishes to optimize the performance of the transistors while simultaneously maintaining process simplicity. The challenge to achieve this in the BiCMOS environment is heightened because the process requirements for the MOSFET and bipolar transistors often conflict with one another. Most of the compromises involved are determined in the design of the front-end of the process. However, since the MOSFET and BJT characteristics are strongly coupled, optimization of both devices can only occur at the expense of increased process complexity and the associated manufacturing cost. A thorough device design approach, coupled with the application of a statistically-based device design methodology, becomes critical for evaluating both performance tradeoffs and manufacturability implications.

Keywords

Device Design Bipolar Transistor Current Gain Gate Delay IEDM Tech 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer Science+Business Media New York 1990

Authors and Affiliations

  • J. Teplik
    • 1
  1. 1.Motorola Inc.USA

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