This chapter describes the fault analysis phase of yield simulation. Once defects have been sized and placed on the chip layout, they must be examined to determine what circuit faults, if any, have occurred. Techniques for performing this analysis include local circuit extraction, layer combination analysis, and type-driven analysis. All of the fault analysis methods described here assume that the input layout geometry has been preprocessed to simplify analysis. We begin this chapter by describing this preprocessing phase. We then briefly describing the local circuit extraction and layer combination analysis methods and showing why they are not suitable for our purposes because of poor performance. We then describe the type-driven analysis method which is best suited for our purpose, and used in VLASIC.
KeywordsOpen Circuit Yield Simulation Fault Analysis Material Defect Circuit Fault
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