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Hot-Carrier Degradation Effects for DRAM Circuits

  • Charvaka Duvvury
  • Shian Aur

Abstract

The continued drive to shrink feature sizes for higher density memory chips is leading to an increase in the internal electric fields of MOS transistors. This increase in the fields near the drain junctions eventually leads to trapped charges during hot-carrier generation, which cause degraded MOSFET characteristics, and consequently results in circuit performance degradation. While for technologies of even 2 μm gate lengths, the effects of hot carriers begin to take place, these become more significant below 1.5 μm channel lengths [1]. Consequently, newer technologies involving Lightly Doped Drain (LDD) or Graded Drain transistors have been developed to combat the high electric fields and help reduce the hot carrier reliability threat. These later developments in the source/drain junction of a transistor are now a part of the 1 μm CMOS technology for the present high-density memory chips. However, 256 kb DRAMs built with less than 1.5 μm NMOS technology and the 1 megabit and 4 megabit DRAMs built with 1 μm CMOS technology are all susceptible to hot carrier stress degradation. Therefore, a clear understanding of not only the transistor degradation, but also its influence on circuit performance, is needed.

Keywords

Stress Time NMOS Transistor Substrate Current Threshold Voltage Shift CMOS Inverter 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Van Nostrand Reinhold 1992

Authors and Affiliations

  • Charvaka Duvvury
    • 1
  • Shian Aur
    • 1
  1. 1.Texas InstrumentsDallasUSA

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