Hot-Carrier Degradation Effects for DRAM Circuits

  • Charvaka Duvvury
  • Shian Aur


The continued drive to shrink feature sizes for higher density memory chips is leading to an increase in the internal electric fields of MOS transistors. This increase in the fields near the drain junctions eventually leads to trapped charges during hot-carrier generation, which cause degraded MOSFET characteristics, and consequently results in circuit performance degradation. While for technologies of even 2 μm gate lengths, the effects of hot carriers begin to take place, these become more significant below 1.5 μm channel lengths [1]. Consequently, newer technologies involving Lightly Doped Drain (LDD) or Graded Drain transistors have been developed to combat the high electric fields and help reduce the hot carrier reliability threat. These later developments in the source/drain junction of a transistor are now a part of the 1 μm CMOS technology for the present high-density memory chips. However, 256 kb DRAMs built with less than 1.5 μm NMOS technology and the 1 megabit and 4 megabit DRAMs built with 1 μm CMOS technology are all susceptible to hot carrier stress degradation. Therefore, a clear understanding of not only the transistor degradation, but also its influence on circuit performance, is needed.


Stress Time NMOS Transistor Substrate Current Threshold Voltage Shift CMOS Inverter 
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  1. 1.
    T. H. Ning, P. W. Cook, R. H. Denard, C. M. Osburn, S. E. Schuster, and H. N. Yu. “1 μm MOSFET VLSI technology: Part 5.” IEE Elec. Dev., vol ED-26, p. 346, 1979.CrossRefGoogle Scholar
  2. 2.
    Fu-Chie Hsu, John Hui, and Kuang Yi Chiu. “Hot electron degradation in submicron VLSI.” IEDM Tech. Dig., p. 48, 1986.Google Scholar
  3. 3.
    James S. Ni. “Modeling of hot electron effects on the device parameters for circuit simulation.” IEDM Tech. Dig., p. 738, 1986.Google Scholar
  4. 4.
    C. Duvvury, D. Redwine, H. Kitagawa, R. Haas, Y. Chung, C. Bydler, and A. Hyslop. “Impact of hot-carriers on DRAM circuits.” 1987 Int. Reliability Physics Symp., p. 201.Google Scholar
  5. 5.
    E. C. Cahoon, K. Thronwell, P. Tsai, T. Gukelberger, J. Sylvestri, and J. Orro. “Hot-electron-induced retention time degradation in MOS dynamic RAMs.” IRPS Proc, 1986.Google Scholar
  6. 6.
    S. Aur, D. E. Hocevar, and P. Yang. “Circuit hot electron effect simulation.” Tech. Dig. of 1987 Int. Electron Devices Meeting, p. 498.Google Scholar
  7. 7.
    C. Hu. “Reliability by design.” SRC Topical Research ConferenceReliability of VLSI Circuits, Austin, TX, March 1987.Google Scholar
  8. 8.
    E. Takeda. “Hot carrier and wear-out phenomena in submicron VLSIs.” 1985 VLSI Symp., p. 2 and references therein.Google Scholar
  9. 9.
    W. Weber and G. Dorda. “Degradation of nMOS transistors after pulse stress.” IEEE Elec. Dev. Lett., EDL-5, p. 518, Dec. 1984.CrossRefGoogle Scholar
  10. 10.
    K.-L. Chen, S. Sailer, and R. Shah. “The case of AC stress in the hot-carrier effect.” IEEE Trans. Elec. Dev., vol. ED-33, p. 424, Mar. 1986.Google Scholar
  11. 11.
    T. Horiuchi, H. Mikoshiba, K. Nakamura, and K. Hamano. “A simple method to evaluate device lifetime due to hot-carrier effect under dynamic stress.” IEEE Elec. Dev. Lett., Vol. EDL-7, p. 337, June 1986.CrossRefGoogle Scholar
  12. 12.
    S. Aur. “Kinetics of hot carrier effects for circuit simulation.” Reliability Physics 27th Proc., 1989, p. 88.Google Scholar
  13. 13.
    C. Hu, S. C. Tarn, F.-C. Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill. “Hot-electron-induced MOSFET degradation—Model, monitor, improvement.” IEEE J. Solid-state Circuits, Vol. SC-20, p. 295, Feb. 1985.Google Scholar
  14. 14.
    C. Duvvury, D. Baglee, M. C. Smayling, and M. P. Duane. “Series resistance modeling for optimum design of LDD transistors. IEDM Tech. Dig., p. 388, 1983.Google Scholar
  15. 15.
    J. M. Pimbley. “A measurement method for the increase of digital switching time due to hot electron stress.” IEEE Elec. Dev. Lett., vol. EDL-6, p. 366, 1985.Google Scholar
  16. 16.
    T. Y. Chan, J. Chen, P. K. Ko, and C. Hu. “The impact of gate-induced leakage on MOSFET scaling.” IEDM Tech. Dig., p. 718, 1987.Google Scholar
  17. 17.
    C. Duvvury, D. J. Redwine, and H. J. Stiegler. “Leakage current degradation in n-MOSFETs due to hot-electron stress.” IEEE Elec. Dev. Lett., vol. EDL-9, pp. 579–581, 1988.Google Scholar
  18. 18.
    T. Sakurai, K. Nogami, M. Kakumu, and T. Iizuka. “Hot-carrier generation in submicrometer VLSI environment.” IEEE J. Solid-State Circuits, Vol. SC-21,pp. 187–191, Feb. 1986.Google Scholar
  19. 19.
    S. Aur, D. E. Hocevar, and P. Yang. “HOTRON—A circuit hot electron effect simulator.” Technical Digest of the 1987 Int. Conference on CAD, p. 256.Google Scholar
  20. 20.
    C. Duvvury. “A guide to short-channel effects in MOSFETs.” IEEE Circ. and Dev., vol. 2, p. 6, 1986.Google Scholar
  21. 21.
    S. Aur, P. Yang, P. Pattnaik, and P. K. Chatterjee. “Modeling of hot carrier effects for LDD MOSFETs.” 1985 Symp. on VLSI Technology, p. 112.Google Scholar
  22. 22.
    E. Takeda. “Hot-carrier effects in submicrometer MOS VLSIs.” IEEE Proc., Vol. 131, Pt. 1, No. 5, p. 153, Oct. 1984.Google Scholar
  23. 23.
    P. Yang and S. Aur. “Modeling of device lifetime due to hot carrier effects.” 1985 Intl. Symp. on VLSI Technology, Systems and Applications, p. 227.Google Scholar
  24. 24.
    S. Aur, C. Duvvury, H. Mcadams, and C. Perrin. “Identification of DRAM Sense-Amplifier Imbalance Using Hot-Carrier Evaluation.” IEEE J. Solid-State Circuits, Vol. 27, No. 3, p. 451, March 1992.CrossRefGoogle Scholar
  25. 25.
    S. Aur, A. Chatterjee, and T. Polgreen. “ESD latent damage and hot electron reliability.” IEEE Trans. Elec. Dev., vol. 35, p. 2189, Dec. 1988.CrossRefGoogle Scholar
  26. 26.
    G. C. Holmes. “An investigation into the effects of low-voltage ESD transients on MOSFET.” 1985 EOS/ESD Symp. Proc., p. 170.Google Scholar
  27. 27.
    C. Duvvury, R. N. Rountree, and O. Adams. “Internal chip ESD phenomena beyond the protection circuit.” Reliability Physics 26th Proc., 1988, p. 19.Google Scholar
  28. 28.
    J. S. Brugler and P. G. A. Jespers. “Charge pumping in MOS devices.” IEEE Trans. Elec. Dev., vol. ED-16, p. 297, Mar. 1969.CrossRefGoogle Scholar
  29. 29.
    Guido Groeseneken et al. “A reliable approach to charge-pumping measurements in MOS transistors.” IEEE Trans. Elec. Dev., vol. ED-31, p. 42, Jan. 1984.CrossRefGoogle Scholar
  30. 30.
    D. Krakauer and K. Mistry. “On latency and physical mechanisms underlying gate oxide damage during ESD events in n-channel MOSFETs. EOS/ESD Symp., 1989.Google Scholar
  31. 31.
    F. Matsuoka et al. “Analysis of hot-carrier-induced degradation mode on p-MOSFETs.” IEEE Trans. Elec. Dev., vol. 37, p. 1487, June 1990.CrossRefGoogle Scholar
  32. 32.
    M. Koyanagi et al. “Investigation and reduction of hot-electron-induced punchthrough (HEIP) effects in submicron MOSFETs.” IEDM Tech. Dig., p. 722, 1986.Google Scholar
  33. 33.
    T. H. Ning. “Emission probability of hot-electrons from silicon into silicon dioxide.” J. Appl. Phys., vol. 48, pp. 286–275, 1977.CrossRefGoogle Scholar
  34. 34.
    M. C. Parris, K. P. Roenker, T. T. Yuliasto, and J. H. Nevin. “Hot carrier effects on submicron MOSFETs and their implications for VLSI circuit design.” Proc. IEEE National Aerospace and Electronics Conf., vol. 1, no. 2–9, 1984.Google Scholar

Copyright information

© Van Nostrand Reinhold 1992

Authors and Affiliations

  • Charvaka Duvvury
    • 1
  • Shian Aur
    • 1
  1. 1.Texas InstrumentsDallasUSA

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