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A Clock Methodology for High-Performance Microprocessors

  • Keith M. Carrig
  • Albert M. Chu
  • Frank D. Ferraiolo
  • John G. Petrovick
  • P. Andrew Scott
  • Richard J. Weiss

Abstract

This paper discusses an effective clock methodology for the design of high-performance microprocessors. Key attributes include the clustering and balancing of clock loads, multiple clock domains, a balanced clock router with variable width wires to minimize skew, hierarchical clock wiring, automated verification, an interface to the Cadence Design Framework IITM environment, and a complete network model of the clock distribution, including loads. This clock methodology enabled creation of the entire clock network, including verification, in less than three days with approximately 180 ps of skew.

Keywords

Clock Tree Clock Distribution Custom Macrocells Reduce Development Time Clock Region 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1997

Authors and Affiliations

  • Keith M. Carrig
    • 1
  • Albert M. Chu
    • 1
  • Frank D. Ferraiolo
    • 1
    • 1
  • John G. Petrovick
    • 1
  • P. Andrew Scott
    • 2
  • Richard J. Weiss
    • 3
  1. 1.IBM Microelectronics DivisionEssex JunctionUSA
  2. 2.Cadence Design SystemsSan JoseUSA
  3. 3.First PASSNW Palm BayUSA

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