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Practical Bounded-Skew Clock Routing

  • Andrew B. Kahng
  • C.-W. Albert Tsao

Abstract

In Clock routing research, such practical considerations as hierarchical buffering, rise-time and overshoot constraints, obstacle- and legal location-checking, varying layer parasitics and congestion, and even the underlying design flow are often ignored. This paper explores directions in which traditional formulations can be extended so that the resulting algorithms are more useful in production design environments. Specifically, the following issues are addressed: (i) clock routing for varying layer parasitics with non-zero via parasitics; (ii) obstacle-avoidance clock routing; and (iii) hierarchical buffered tree synthesis. We develop new theoretical analyses and heuristics, and present experimental results that validate our new approaches.

Keywords

Steiner Tree Boundary Segment Clock Tree Merging Point Merging Region 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1997

Authors and Affiliations

  • Andrew B. Kahng
    • 1
  • C.-W. Albert Tsao
    • 1
  1. 1.Computer Science Dept.UCLALos AngelesUSA

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