Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology
Recent advances in integrated circuit technology have imposed new requirements on the chip physical design process. At the same time that performance requirements are increasing, the effects of wiring on delay are becoming more significant. Larger chips are also increasing the chip wiring demand, and the ability to efficiently process these large chips in reasonable time and space requires new capabilities from the physical design tools. Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as required to support additional technologies and larger data volumes. To meet timing requirements, placement may be run iteratively using successively refined timing-derived constraints. Chip optimization tools are used to physically optimize the clock trees and scan connections, both to improve clock skew and to improve wirability. These tools interchange sinks of equivalent nets, move and create parallel copies of clock buffers, add load circuits to balance clock net loads, and generate balanced clock tree routes. Routing is done using a grid-based, technologyindependent router that has been used over the years to wire chips. There are numerous user controls for specifying router behavior in particular areas and on particular interconnection levels, as well as adjacency restrictions.
KeywordsPhysical Design Large Chip Clock Tree Clock Distribution Clock Distribution Network
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- 1.J.Y. Sayah, R. Gupta, D. Sherlekar, P.S. Honsinger, S.W. Bollinger, H.-H. Chen, S. DasGupta, E.P. Hsieh, E.J. Hughes, A.D. Huber, Z.M. Kurzum, V.B. Rao, T. Tabtieng, V. Valijan, D.Y. Yang, and J. Apte, “Design planning for high-performance ASICs,IBM J. Res. Develop., Vol. 40, No. 3, pp. 431–452.Google Scholar
- 2.R.S. Belanger, D.P. Conrady, P.S. Honsinger, T.J. Lavery, S.J. Rothman, E.C. Schanzenbach, D. Sitaram, C.R. Selinger, R.E. DuBios, G.W. Mahoney, and G.F. Miceli, “Enhanced chip/package design for the IBM ES/9000,Proceedings of the IEEE International Conference on Computer Design, pp. 544549, 1991.Google Scholar
- 4.R.F. Lembach, J.F. Borkenhagen, J.R. Elliot, and R.A. Schmidt, “VLSI design automation for the application system/400,Pmceedings of the IEEE International Conference on Computer Design, pp. 444–447, 1991.Google Scholar
- 6.K.J. Antreich, F.M. Johannes, and F.H. Kirsch, “A new approach for solving the placement problem using force models,Proceedings of the IEEE Symposium on Circuits and Systems, pp. 481–486, 1982.Google Scholar
- 7.R.-S. Tsay, E.S. Kuh, and C.-P. Hsu, “PROUD: A fast sea-ofgates placement algorithm,Proceedings of the 25th ACM/IEEE Design Automation Conference, pp. 318–323, 1988.Google Scholar
- 8.K. Narayan, “Clock system design for high speed integrated circuits,IEEE/ERA Wescon/92 Conference Record, pp. 21–24, 1992.Google Scholar
- 9.H.B. Bakoglu, J.T. Walker, and J.D. Meindl, “A symmetric clock distribution tree and optimized high speed interconnections for reduced clock skew in ULSI and WSI circuits,Proceedings of the IEEE International Conference on Computer Design, pp. 118–122, 1986.Google Scholar
- 10.K.M. Carrig, D.J. Hathaway, K.W. Lallier, J.H. Panner, and T.W. Sehr, “Method and apparatus for making a skew-controlled signal distribution network,U.S. Patent 5,339, 253, 1994.Google Scholar
- 12.K.D. Boese and A.B. Kahng, “Zero-skew clock routing trees with minimum wirelength,Proceedings of the Fifth Annual IEEE International ASIC Conference and Exhibit, pp. 17–21, 1992.Google Scholar
- 13.S. Pullela, N. Menezes, J. Omar, and L.T. Pillage, “Skew and delay optimization for reliable buffered clock trees,Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 556–562, 1993.Google Scholar
- 14.R. Kent Dybvig, The Scheme Programming Language, Prentice-Hall, Inc., Englewood Cliffs, NJ, 1987.Google Scholar
- 15.C.W. Koburger III, W.F. Clark, J.W. Adkisson, E. Adler, P.E. Bakeman, A.S. Bergendahl, A.B. Botula, W. Chang, B. Davari, J.H. Givens, H.H. Hansen, S.J. Holmes, D.V. Horak, C.H. Lam, J.B. Lasky, S.E. Luce, R.W. Mann, G.L. Miles, J.S. Nakos, E.J. Nowak, G. Shahidi, Y. Taur, F.R. hite, and M.R. Wordeman, “A half-micron CMOS logic generation,IBM J. Res. Develop. Vol. 39, Nos. 1 /2, pp. 215–227, Jan./March 1995.CrossRefGoogle Scholar