Clock Distribution Methodology for PowerPC™ Microprocessors

  • Shantanu Ganguly
  • Daksh Lehther
  • Satyamurthy Pullela


Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this context. We describe the clock design methodology and techniques used in the design of clock distribution networks for PowerPCTM microprocessors that aim at alleviating some of these problems.


Central Network Clock Signal Clock Phase Clock Distribution Wire Width 
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Copyright information

© Kluwer Academic Publishers 1997

Authors and Affiliations

  • Shantanu Ganguly
    • 1
  • Daksh Lehther
    • 1
  • Satyamurthy Pullela
    • 2
  1. 1.Somerset Design CenterMotorolaAustinUSA
  2. 2.Unified Design System LaboratoryMotorolaAustinUSA

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