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Buffered Clock Tree Synthesis with Non-Zero Clock Skew Scheduling for Increased Tolerance to Process Parameter Variations

  • José Luis Neves
  • Eby G. Friedman

Abstract

An integrated top-down design system is presented in this paper for synthesizing clock distribution networks for application to synchronous digital systems. The timing behavior of a synchronous digital circuit is obtained from the register transfer level description of the circuit, and used to determine a non-zero clock skew schedule which reduces the clock period as compared to zero skew-based approaches. Concurrently, the permissible range of clock skew for each local data path is calculated to determine the maximum allowed variation of the scheduled clock skew such that no synchronization failures occur. The choice of clock skew values considers several design objectives, such as minimizing the effects of process parameter variations, imposing a zero clock skew constraint among the input and output registers, and constraining the permissible range of each local data path to a minimum value.

The clock skew schedule and the worst case variation of the primary process parameters are used to determine the hierarchical topology of the clock distribution network, defining the number of levels and branches of the clock tree and the delay associated with each branch. The delay of each branch of the clock tree is physically implemented with distributed buffers targeted in CMOS technology using a circuit model that integrates short-channel devices with the signal waveform shape and the characteristics of the clock tree interconnect. A bottom-up approach for calculating the worst case variation of the clock skew due to process parameter variations is integrated with the top-down synthesis system. Thus, the local clock skews and a clock distribution network are obtained which are more tolerant to process parameter variations.

This methodology and related algorithms have been demonstrated on several MCNC/ISCAS-89 benchmark circuits. Increases in system-wide clock frequency of up to 43% as compared with zero clock skew implementations are shown. Furthermore, examples of clock distribution networks that exploit intentional localized clock skew are presented which are tolerant to process parameter variations with worst case clock skew variations of up to 30%.

Keywords

Data Path Clock Period Feedback Path Benchmark Circuit Permissible Range 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    S. Pullela, N. Menezes, J. Omar, and L.T. Pillage, “Skew and delay optimization for reliable buffered clock trees,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 556–562, Nov. 1993.Google Scholar
  2. 2.
    Q. Zhu, W.W.-M. Dai, and J.G. Xi, “Optimal sizing of highspeed clock networks based on distributed RC and lossy transmission line models,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 628–633, Nov. 1993.Google Scholar
  3. 3.
    J. Cong and K.-S. Leung, “Optimal wiresizing under the distributed elmore delay model,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 634–639, Nov. 1993.Google Scholar
  4. 4.
    J. Cong and C.-K. Koh, “Simultaneous driver and wire sizing for performance and power optimization,” IEEE Transactions on VLSI Systems, Vol. VLSI-2, No. 4, pp. 408–425, Dec. 1994.CrossRefGoogle Scholar
  5. 5.
    H.B. Bakoglu, J.T. Walker, and J.D. Meindl, “A symmetric clock-distribution tree and optimized high-speed interconnections for reduced clock skew in ULSI and WSI circuits,” Proceedings of the IEEE International Conference on Computer Design, pp. 118–122, Oct. 1986.Google Scholar
  6. 6.
    T.-H. Chao, Y.-C. Hsu, J.-M. Ho, K.D. Boese, and A.B. Kahng, “Zero skew clock routing with minimum wirelength,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. CAS-39, No. 11, pp. 799–814, Nov. 1992.CrossRefGoogle Scholar
  7. 7.
    R.-S. Tsay, “An exact zero-skew clock routing algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. CAD-12, No. 2, pp. 242–249, Feb. 1993.CrossRefGoogle Scholar
  8. 8.
    S. Lin and C.K. Wong, “Process-variation-tolerant clock skew minimization,” Proceedings of the IEEE International Conference on Computer-Aided Design, pp. 284–288, Nov. 1994.Google Scholar
  9. 9.
    M. Shoji, “Elimination of process-dependent clock skew in CMOS VLSI,” IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, pp. 875–880, Oct. 1986.CrossRefGoogle Scholar
  10. 10.
    E.G. Friedman, Clock Distribution Networks in VLSI Circuits and System, IEEE Press, 1995.Google Scholar
  11. 11.
    J.P. Fishbum, “Clock skew optimization,” IEEE Transactions on Computers, Vol. C-39, No. 7, pp. 945–951, July 1990.CrossRefGoogle Scholar
  12. 12.
    R.B. Deokar and S. Sapatnekar, “A graph-theoretic approach to clock skew optimization,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 407–410, May 1994.Google Scholar
  13. 13.
    J.L. Neves and E.G. Friedman, “Design methodology for synthesizing clock distribution networks exploiting non-zero localized clock skew,” IEEE Transactions on VLSI Systems, Vol. VLSI-4, No. 2, pp. 286–291, June 1996.CrossRefGoogle Scholar
  14. 14.
    J.L. Neves and E.G. Friedman, “Synthesizing distributed buffer clock trees for high performance ASICs,” Proceedings of the IEEE ASIC Conference, pp. 126–129, Sept. 1994.Google Scholar
  15. 15.
    E.G. Friedman, “Latching characteristics of a CMOS bistable register,” IEEE Transactions on Circuits and Systems—I: Fundamental Theory and Applications, Vol. CAS I-40, No. 12, pp. 902–908, Dec. 1993.CrossRefGoogle Scholar
  16. 16.
    K.A. Sakallah, T.N. Mudge, and O.A. Olukotun, “CheckTc and minTc: Timing verification and optimal clocking of synchronous digital circuits,” Proceedings of the IEEE/ACM Design Automation Conference, pp. 111–117, June 1990.Google Scholar
  17. 17.
    T.G. Szymanski, “Computing optimal clock schedules,” Proceedings of the IEEE/ACM Design Automation Conference, pp. 399–404, June 1992.Google Scholar
  18. 18.
    J.L. Neves and E.G. Friedman, “Optimal clock skew scheduling tolerant to process variations,” Proceedings of the ACM/IEEE Design Automation Conference, pp. 623–628, June 1996.Google Scholar
  19. 19.
    J.L. Neves, “Synthesis of Clock Distribution Networks for High Performance VLSUULSI-Based Synchronous Digital Systems,” Ph.D. Dissertation, University of Rochester, Dec. 1995.Google Scholar
  20. 20.
    J.L. Neves and E.G. Friedman, “Topological design of clock distribution networks based on non-zero clock skew specifications,” Proceedings of the IEEE Midwest Symposium on Circuits and Systems, pp. 461–471, Aug. 1993.Google Scholar
  21. 21.
    S.Dhar and M.A. Franklin, “Optimum buffer circuits for driving long uniform lines,” IEEE Journal of Solid State Circuits, Vol. SC-26, No. 1, pp. 32–40, Jan. 1991.CrossRefGoogle Scholar
  22. 22.
    J.L. Neves and E.G. Friedman, “Circuit synthesis of clock distribution networks based on non-zero clock skew,” Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 4.175–4.178, May 1994.Google Scholar
  23. 23.
    T. Sakurai and A.R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE Journal ofSolid State Circuits, Vol. SC-25, No. 2, pp. 584–594, April 1990.CrossRefGoogle Scholar

Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • José Luis Neves
    • 1
  • Eby G. Friedman
    • 1
  1. 1.Department of Electrical EngineeringUniversity of RochesterRochesterUSA

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