Clocking Optimization and Distribution in Digital Systems with Scheduled Skews
System performance can be improved by employing scheduled skews at flip-flops. This optimization technique is called skewed-clock optimization and has been successfully used in memory designs to achieve high operating frequencies. There are two important issues in developing this optimization technique. The first is the selection of appropriate clock skews to improve system performance. The second is to reliably distribute skewed clocks in the presence of manufacturing and environmental variations. Without the careful selection of clocking times and control of unintentional clock skews, potential system performance might not be achieved. In this paper a theoretical framework is first presented for solving the problem of optimally scheduling skews. A novel selfcalibrating clock distribution scheme is then developed which can automatically track variations and minimize unintentional skews. Clocks with proper skews can be reliably delivered by such a scheme.
KeywordsClock Generator Quantization Error Clock Period Sequential Circuit Reference Clock
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