Clock Skew Optimization for Peak Current Reduction

  • L. Benini
  • P. Vuillod
  • A. Bogliolo
  • G. De Micheli


The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that, for a given clock cycle time, determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern.


Current Profile Combinational Logic Peak Current Reduction Benchmark Circuit Clock Tree 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Kluwer Academic Publishers 1997

Authors and Affiliations

  • L. Benini
    • 1
  • P. Vuillod
    • 1
  • A. Bogliolo
    • 1
    • 2
  • G. De Micheli
    • 1
  1. 1.Computer Systems LaboratoryStanford UniversityStanfordUSA
  2. 2.DEIS, Università di BolognaItaly

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