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Defect Levels Controlling the Behavior of NTD Silicon During Annealing

  • B. Jayant Baliga
  • Andrew O. Evwaraye

Abstract

The variation of the resistivity and minority carrier lifetime has been examined during the annealing of neutron transmutation doped silicon. During each annealing step deep level transient spectroscopy has also been used to detect the presence of deep lying energy levels within the silicon energy gap. By the use of both p- and n- type crystals with doping levels higher than the phosphorus concentration created by the neutron transmutation process, deep levels lying in both the upper and lower half of the energy gap have been measured.

Although the resistivity anneals to its final value at temperatures around 600°C, it has been found that during isochronal annealing, the minority carrier lifetime continues to increase up to annealing temperatures arourid 700°C. Under these annealing conditions, four majority carrier trap levels have been found in the n- type wafers and five majority carrier trap levels have been found in the p-type wafers. Measurements of the minority carrier lifetime as a function of ambient temperature indicate that the lifetime controlling recombination center lies at 0.30 eV below the conduction band in the p-type silicon and at 0.30 eV above the valency band in n-type silicon.

Keywords

Deep Level Minority Carrier Deep Level Transient Spectroscopy Minority Carrier Lifetime Isochronal Annealing 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Plenum Press, New York 1979

Authors and Affiliations

  • B. Jayant Baliga
    • 1
  • Andrew O. Evwaraye
    • 1
  1. 1.Corporate R and D CenterGeneral Electric CompanySchenectadyUSA

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