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Thermal Stress Considerations in Die-Attachment

  • Goran S. Matijasevic
  • Chen Yu Wang
  • Chin C. Lee

Abstract

An important aspect of packaging the semiconductor device is how securely the die is attached to the substrate. The chip is normally bonded onto a substrate or a package using hard solder, soft solder, metal-filled epoxy, or glass.1–3 The package together with the die-bonding layer serves the purposes of heat dissipation, mechanical support, and sometimes electrical conduction. With increasing power requirements of the chip, quality die-attach becomes a special concern. Thermal stress considerations need to be taken into account even in a perfectly executed die-attach where the constituent materials have formed a single entity with no voids. Due to thermal expansion mismatch among the die, the bonding material, and the package, stress is introduced in the cooling step of the bonding process. Stress is generated in the die that may cause cracking. Dynamic stress is also produced in the bonded devices when they are subjected to power cycling, thermal cycling, or thermal shock.

Keywords

Thermal Expansion Coefficient Electronic Packaging Bonding Layer Thermal Shock Test Maximum Normal Stress 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Van Nostrand Reinhold 1993

Authors and Affiliations

  • Goran S. Matijasevic
  • Chen Yu Wang
  • Chin C. Lee

There are no affiliations available

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