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Thermal Stress and Stress-Induced Voiding in Passivated Narrow Line Metallizations on Ceramic Substrates

  • M. A. Korhonen
  • P. Børgesen
  • Che-Yu Li

Abstract

Thermal stresses in metallizations are of current concern in the microelectronics industry. Stress-induced void and hillock formation are the main causes of interconnect failure before service.1–4 Recently there has been a growing concern that stress-induced voids in the interconnect lines, formed during fabrication, may enhance subsequent electromigration damage during the use of the microchips.5,6 For definitiveness we address pure aluminum metallizations on oxidized silicon substrates. The general principles are applicable to other metal hard substrate systems as well, most notably to aluminum and copper alloys on various ceramic substrates. The emphasis of the treatment is on the formation of tensile thermal stresses in the metallization during cooldown from elevated temperatures, and on the relaxation of them by void growth. However, much of the treatment is also applicable to hillock formation under compressive thermal stresses.

Keywords

Thermal Stress Stress Relaxation Void Growth Grain Boundary Slide Ceramic Substrate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Van Nostrand Reinhold 1993

Authors and Affiliations

  • M. A. Korhonen
  • P. Børgesen
  • Che-Yu Li

There are no affiliations available

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