PLAMG: An Automatic PLA Minimizer and Generator for VLSI System Design

  • Cheng Chen
  • Wen Zen Shen
  • Young-Li Lee
  • Li-Wen Shih
  • Yeh Jian Liang


In this paper, we will introduce an Automatic PLA Minimizer and Generator, PLAMG, for VLSI system design, which has been designed and implemented in VAX-11/780 running under UNIX operating system. The PLAMG contains four parts. The first is Bprer which accepts the Boolean Equations as inputs and translates into equivalent truth table. The second part is product minimization which is based on MINI-algorithm. The third part is simple column folding to optimize the given PLA topologically. And finally, the reduced PLA matrix is sent to PLAGEN to generate the NMOS NOR-NOR plane layout automatically. Several examples has been tested and evaluated. The results showed that PLAMG has good performance and is a useful tool for VLSI system design. At the end of the paper, some future extensions and improvements are also discussed.


Topological Optimization Heuristic Algorithm Product Term Truth Table Logic Minimization 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Plenum Press, New York 1985

Authors and Affiliations

  • Cheng Chen
    • 1
  • Wen Zen Shen
    • 2
  • Young-Li Lee
    • 1
  • Li-Wen Shih
    • 1
  • Yeh Jian Liang
    • 1
  1. 1.Dept. of Computer EngineeringNational Chiao Tung UniversityHsin-ChuTaiwan, R.O.C.
  2. 2.Institute of ElectronicsNational Chiao Tung UniversityHsin-ChuTaiwan, R.O.C.

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