A CAD Program for VLSI Placement and Routing
In this paper, a set of algorithms for circuit layout is developed. Algorithms for automatic/interactive placement of standard cell blocks in parallel rows use the concept of blending and repartition. The grouping and linear placement techniques are also used. Constructive-initial placement is interlaced with iterative-improved placement for better results.
Routing is divided into two subproblems; global (loose) routing and channel (detailed) routing. Global routing is used to find a layout topology for the interconnection nets. Graph theory is used to model the layout. Channel routing is used to interconnect nets or subnets within a channel using some novel and constructive methods. Algorithms for both global and channel routing are proposed.
KeywordsPlacement Problem Minimum Steiner Tree Logic Diagram Circuit Layout Forward Pointer
Unable to display preview. Download preview PDF.
- S. Muroga, “VLSI System Design,” John Wiley Company, 1982.Google Scholar
- G. Persky, et al., “LTX-A Minicomputer-Based System for Automated LSI Layout,” Design Automation & Fault-Tolerant Computing, Vol. 1, No. 3, May 1977, pp. 217–256.Google Scholar
- I. Nishioka, et al., “An approach to gate assignment and model placement for printed wiring boards,” Proc. 15th Annual Design Automation Conf., 1978, pp. 60–69.Google Scholar
- M. Hanan and J. M. Kurtzberg, “Placement Techniques,” Chap. 5 in Design Automation of Digital Systems: Theory and Techniques, Vol. 1 (M. A. Breuer, Ed. ), Prentice-Hall, 1972, pp. 213–282.Google Scholar
- M. Hanan, et al., “A Study of Placement Techniques,” Design Automation & Fault-Tolerant Computing,“ Vol. 2, No. 2, May 1978, pp. 145–164.Google Scholar
- D. G. Schweikert, “A 2-dimensional placement algorithm for the layout of electrical circuits,” Proc. 13th Annual Design Automation Conf., 1976, pp. 408–416.Google Scholar
- M. Breuer, “Min-Cut Placement,” Design Automation & Fault-Tolerant Computing,“ Vol. 1, No. 4, Oct. 1977, pp. 343–362.Google Scholar
- B. W. Kernighan and S. Lin, “An efficient procedure for partitioning graphs,” Ball System Technical Journal, Feb. 1970, pp. 291–307.Google Scholar
- D. C. Schmidt and L. E. Duffel, “An iterative algorithm for placement and assignment of integrated circuits,” Proc. 12th Annual Design Automation Conf., 1975, pp. 361–368.Google Scholar
- T. Kambe, et al., “A placement algorithm for polycell LSI and its evaluation,” Proc. 19th Annual Design Automation Conf., 1982, pp. 655–662.Google Scholar
- D. M. Schuler and E. G. Ulrich, “Clustering and linear placement,” Proc. 9th Annual Design Automation Workshop, 1972, pp. 50–56.Google Scholar
- H. Beke and W. Sansen, “CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI,” Proc. 16th Annual Design Automation Conf., 1979, pp. 102–108.Google Scholar
- H. Kanada, K. Okazaki, M. Tachibana, B. Kato, and S. Murai, “Channel order router,” J. Dig. Sys., Vol. 4, Issue 4, 1981, pp. 427–441.Google Scholar
- A. Hashimoto and J. Stevens, “Wire routing by optimizing channel assignment within large apertures,” Proc. 8th Annual Design Automation Conf., 1971, pp. 155–169.Google Scholar
- T. Yoshimura and E. S. Kuh, “Efficient algorithms for channel routing,” IEEE Trans. on CAD & ICAS, Vol. CAD-1, No. 1, Jan. 1982, pp. 25–35.Google Scholar