An Integrated Approach to Design, Implementation, and Testing of Digital Systems
Recent advancements in the micro-electronic technology have made it possible to manufacture digital systems of considerable complexity at a very low per-system cost. Full potential of this manufacturing capability, however, can be utilized only if the associated digital hardware design automation systems can be upgraded to reduce the cost associated with the design process. This is especially true of special purpose low-volume digital systems.
From initial requirement specification, the design of a digital system progresses through several levels of refinements until it reaches the final fabrication phase. A modern digital hardware design automation system must be able to support all phases of design activities, including testing, from a single description of the digital system which is to be designed. Since the complexity of digital systems is ever-increasing it is necessary that the design automation system provides an abstraction mechanism for clear, concise and unambiguous description of the digital system. Such abstraction is provided by the computer hardware description languages (CHDLs).
This paper discusses the design and implementation of a CHDL based automation system that provides an integrated environment to support all phases of design activities from initial specification to final fabrication and testing of digital system. Current industrial applications of the automation system and future research plans will also be discussed.
KeywordsDigital System Design Automation System Sequential Circuit Register Transfer Level Hardware Description Language
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- M. R. Barbacci, “Instruction set processor specifications (ISPS): the notation and its application,” IEEE Trans. on Computers, vol. C-30, pp. 24–40, Jan. 1981.Google Scholar
- J. E. Belt, “An heuristic approach to test sequence generation for AHPL described sequential circuits,” Ph.D. dissertation, University of Arizona, 1973.Google Scholar
- E. A. Carter, “Fault test generation for sequential circuits described in AHPL,” Ph.D. dissertation, University of Arizona, 1973.Google Scholar
- C. H. Chiang, F. Hill, A. Mohseni, and D. Chen, “Fault detection test generation at the register transfer level,” in Proc. IEEE First Annual Phoenix Conf. on Computers and Communications, pp. 58–63, May 1982.Google Scholar
- Y. Chu, “An Algol-like computer design language,” Communications ACM, pp. 607–615, October 1965.Google Scholar
- F. J. Hill, “Updating AHPL,” in Proc. 1975 Int. Symp. on Hardware Description Languages and Their Applications,“ pp. 22–29, Sept. 1975.Google Scholar
- F. J. Hill and G. R. Peterson, Digital Systems: Hardware Organization and Design, 2nd ed., John Wiley & Sons, New York, 1978.Google Scholar
- B. M. Huey, “Search directing heuristics for sequential circuit test system ( SCIRTSS),” Ph.D. dissertation, University of Arizona, 1973.Google Scholar
- C. R. Kine, “An organization for checking experiments on sequential circuits,” IEEE Trans. on Elect. Computers, Vol. EC-15, pp. 113–115, Feb. 1966.Google Scholar
- M. Masud, “A modular implementation of a digital hardware design automation system,” Ph.D. dissertation, University of Arizona, 1981.Google Scholar
- C. Mead and L. Conway, Introduction to VLSI System, Addison Wesley, Massachusetts, 1981.Google Scholar
- Z. Navabi, M. Masud, W. Knapp, and F. Hill, “Impact of VLSI technology on the hardware description language AHPL,” in Proc. 1980 Conf. on Circuits and Computers, 1980.Google Scholar
- R. Piloty, “Segmentation constructs for RTS III,” in Proc. 1975 Int. Symp. on Hardware Description Languages and Their Applications,“ pp. 115–124, Sept. 1975.Google Scholar
- K. Wacks, F. Hill, M. Masud, and P. deBruyn Kops, “An integrated system for LSI device modeling,” in Proc. Automatic Testing 80, Paris, France, Sept. 1980.Google Scholar