# The Mapping Problem in Parallel Computation

Chapter

## Abstract

The *mapping problem* is the process of implementing a computational task on a target architecture in order to maximize some performance metric. This problem is fundamental to parallel computation and researchers have taken a number of different approaches to solve it. This paper surveys and illustrates the characteristics-based approach, language-based approach, linear algebra-based approach and graph-based approach in current research on the mapping problem. Some general themes of these approaches are discussed and contrasted in the last section.

## Keywords

Parallel Algorithm Systolic Array Task Graph Mapping Problem Graph Expansion
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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## References

- [1]AHO, A., HOPCROFT, J. and J. ULLMAN,
*Data Structures and Algorithms*, Addison Wesley, 1983.Google Scholar - [2]ALLEN, J. and K. KENNEDY,
*PFC: A Program to Convert Fortran to Parallel Form*, Proceedings of the IBM Conference on Parallel Computers and Scientific Computations, March, 1982.Google Scholar - [3]BERMAN, F.,
*Experience with an Automatic Solution to the Mapping Problem*, The Characteristics of Parallel Algorithms, edited by L. Jamieson, D. Gannon and R. Douglass, MIT Press, Cambridge, Mass., 1987.Google Scholar - [4]BERMAN, F., GOODRICH, M., KOELBEL, C., ROBISON, W. and K. SHOWELL,
*Prep-P: A Mapping Preprocessor for CHiP Architectures*, Proceedings of the 1985 International Conference on Parallel Processing, Pheasant Run, Illinois.Google Scholar - [5]BERMAN, F. et al., Prep-P Internal Documentation, unpublished project documentation.Google Scholar
- [6]BERMAN and L. SNYDER,
*Mapping Parallel Algorithms into Parallel Architectures*, extended abstract, Proceedings of the 1984 International Conference on Parallel Processing, Bellaire, Michigan.Google Scholar - [7]BERMAN, F. and L. SNYDER,
*Mapping Parallel Algorithms into Parallel Architectures*Journal of Parallel and Distributed Computing, to appear.Google Scholar - [8]BOKHARI, S.,
*On the Mapping Problem*, IEEE Transactions on Computers, Vol. C-30, March, 1981.Google Scholar - [9]BROWNE, J.,
*Formulation and Programming of Parallel Computations: A Unified Approach*, Proceedings of the 1985 International Conference on Parallel Processing, Pheasant Run, Illinois.Google Scholar - [10]CAPELLO, P. and K. STEIGLITZ,
*Unifying VLSI Array Design with Linear Transformations of Space-Time*, Advances in Computing Research, Vol. 2, JAI Press, 1984.Google Scholar - [11]CUNY, J. and D. BAILEY,
*Graph Grammar Based Specification of Intercon-**nection Structures*, Department of Computer and Information Science Technical Report A-86–23, University of Massachussetts at Amherst, July, 1986.Google Scholar - [12]DEGROOT, D.,
*Partitioning Job Structures for SW-Banyan Networks*, Proceed- ings of the 1983 International Conference on Parallel Processing, Bellaire, Michigan.Google Scholar - [13]DELP, E., SIEGEL, H.J., WHINSTON, A. and L. JAMIESON,
*An Intelligent Operating System for Executing Image Understanding Tasks on a Reconfigurable Parallel Architecture*, Proceedings of the IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Miami, Fl., 1985.Google Scholar - [14]FISHBURN, J. and R. FINKEL,
*Quotient Networks*, IEEE Transactions on Computers, Vol. C-31, April, 1982.Google Scholar - [15]FORTES, J. and D. MOLDOVAN,
*Parallelism Detection and Transformation Techniques Useful for VLSI Algorithms*, Journal of Parallel and Distributed Computing, Vol. 2, August, 1985.Google Scholar - [16]GAREY, M. and D. JOHNSON,
*Computers and Intractability, A Guide to NP-**Completeness*, W.H. Freeman and Company, 1979.Google Scholar - [15]HADEN, P. and F. BERMAN, A
*Comparative Study of Mapping Algorithms for an Automated Parallel Programming Environment*Department of Computer Science Technical Report CS-088, University of California, San Diego.Google Scholar - [18]JAMIESON, L.,
*Characterizing Parallel Algorithms*, The Characteristics of Parallel Algorithms edited by L. Jamieson, D. Gannon and R. Douglass, MIT Press, Cambridge, Mass., 1987.Google Scholar - [19]KERNIGHAN, B. and S. LIN, An
*Efficient Heuristic Procedure for Partitioning**Graphs*, Bell System Technical Journal, February, 1970.Google Scholar - [20]KUCK, D. et.al, The Effects of Program Restructuring, Algorithm Change and Architecture Choice on Program Performance,
*Proceedings of the 1984 International Conference on Parallel Processing, Bellaire, Michigan*.Google Scholar - [21]KUCK, D., KUHN, R., LEASURE, B. and M. WOLFE, The Structure of an Advanced Retargetable Vectorizer,
*Tutorial on Supercomputers, Designs and Applications, edited by K. Hwang, IEEE Press*, New York, 1984.Google Scholar - [22]KUNG, S.Y.
*On Supercomputing with Systolic!Wavefront Array Processors*, Proceedings of the IEEE, Vol. 72, July, 1984.Google Scholar - [23]MCGRAW, J., SKEDZIELEWSKI, S.
*et. al*, SISAL: Streams and Iteration in a Single-Assignment Language,*M-146, Lawrence Livermore National Laboratory*, March, 1985.Google Scholar - [24]MOLDOVAN, D. and J. FORTES,
*Partitioning Algorithms for Fixed Size VLSI Architectures*, Department of Electrical Engineering-Systems Technical Report PPP 83–5, University of Southern California, 1983.Google Scholar - [25]NELSON, P. and L. SNYDER,
*Programming Solutions to the Algorithm Contraction Problem*, Proceedings of the 1986 International Conference on Parallel Processing, Pheasant Run, Illinois.Google Scholar - [26]PADUA, D. and M. WOLFE, Advanced Compiler Optimizations for Supercomputers,
*Communications of the ACM, Volume**29, Number 12*, December, 1986.Google Scholar - [27]ROSE, D. and F. BERMAN,
*Mapping with External I/O: A Case Study*, Proceedings of the 1987 International Conference on Parallel Processing, Pheasant Run, Illinois.Google Scholar - [28]SARKAR, V., Partitioning and Scheduling Parallel Programs for Execution on Multiprocessors,
*Ph.D. Dissertation, Computer Systems Laboratory Technical Report No. CSL-TR-87–328, Stanford University*, April 1987.Google Scholar - [29]SARKAR, V. and J. HENNESSY,Compile-time Partitioning and Scheduling of Parallel Programs,
*Proceedings of the*1986 SIGPLAN Symposium on Compiler Construction.Google Scholar - [30]SEGALL, Z. and L. SNYDER, editors,
*Proceedings of the NSF-CMU Workshop on Performance-Efficient Parallel Programming*, Seven Springs, Champion, Pa., Department of Computer Science Technical Report, Carnegie-Mellon University, 1987.Google Scholar - [31]SKEDZIELEWSKI, S. and J. GLAUERT, IF1 - An Intermediate Form for Applicative Languages,
*Version 1.0, M-170, Lawrence Livermore National Laboratory*, July, 1985.Google Scholar - [32]SNYDER, L.,
*Type Architectures, Shared Memory, and the Corollary of Modest Potential*, Annual Review of Computer Science, 1: 289–317, 1986.CrossRefGoogle Scholar - [33]SNYDER, L.,
*Introduction to the Configurable, Highly Parallel Computer*, Computer, January, 1982.Google Scholar - [34]SNYDER, L.,
*Introduction to the Poker Parallel Programming Environment*, Proceedings of the 1983 International Conference on Parallel Processing, Bellaire, Michigan.Google Scholar - [35]STONE, H.,
*Parallel Processing with the Perfect Shuffle*, IEEE Transactions on Computers, C-20: 2, 1971.Google Scholar - [36]ULLMAN, J., Computational Aspects of VLSI,
*Computer Science Press*, 1984.Google Scholar - [37]VARMAN, P. and I. RAMAKRISHNAN,
*On Matrix Multiplication Using Array Processors*, Lecture Notes in Computer Science: Proceedings of the 12th International Conference on Automata, Languages and Programming, Springer-Verlag, Volume 194, July, 1985.Google Scholar

## Copyright information

© Springer-Verlag New York Inc. 1988