On Validating Parallel Architectures via Graph Embeddings

  • Arnold L. Rosenberg


A viable multi-purpose parallel architecture must exhibit many qualities, including: technological feasibility, low communication overhead, robustness in the face of faults, and programmability. The maturity and reliability of techniques for detecting and studying these desiderata decrease rapidly in the order of their listing. The issues of technological feasibility and communication overhead are relatively well understood; progress is being made on the problem of detecting and enhancing the robustness of proposed architectures; but the issue of programmability has not yet even been formulated in a generally accepted way. We extrapolate here from joint work with S. N. Bhatt, F. R. K. Chung, L. S. Heath, and F. T. Leighton, to propose an avenue for assessing the programmability of a proposed parallel architecture, using the formal tool of graph embeddings. As is common, we represent the communication structure of a parallel architecture as an undirected graph, and we seek efficient embeddings of a variety of specific graph families in the architecture graph. We choose the graph families to abstract the intertask dependency structures of popular algorithmic strategies, such as divide-and-conquer and convolution. We illustrate the approach by describing recent studies of optimal embeddings in the Hypercube architecture.


Binary Tree Rectangular Grid Parallel Architecture Graph Embedding Technological Feasibility 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Plenum Press, New York 1988

Authors and Affiliations

  • Arnold L. Rosenberg
    • 1
  1. 1.University of MassachusettsAmherstUSA

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