Piggyback WSI GaAs Systolic Engine

  • H. Merchant
  • H. Greub
  • R. Philhower
  • N. Majid
  • J. F. McDonald


GaAs digital circuits have been much heralded as a means for achieving high computational throughput rates. For example, recently Hughes has published accounts of a flip-flop exhibiting toggle rates approaching 20 GHz using 0.2 micron BFL-CEL MESFET logic operating at room temperature. This impressive performance must, however, be taken in the context of the severe yield problems which inhibit the use of this technology in a cost effective manner in large systems. This leads to the fabrication of big systems using a large number of relatively small dies. Use of conventional packaging for such small dies then introduces parasitics which largely negate the performance improvements promised by the underlying GaAs technology. In this paper we examine one approach to packaging a large number of small GaAs circuits to implement a system of 1000 heavily pipelined systolic processors each operating at a rate of 1 billion floating point operations a second resulting in a sustained throughput of 1000 GFLOPS. This stunning performance could be accomplished using a package with a volume of a few cubic feet, and dissipating only about 10 KW of power. The impact on aerospace tactical and strategic signal processing applications of such a technology could be substantial.


Floating Point Operation Clock Distribution Wafer Scale Wiring Yield Clock Distribution Network 


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  1. [1]
    McDonald, J.F., Donlan, Capt. B.J., Steinvorth, R.H., Greub, H., Dhodhi, M., Kim, J.S., and Bergendahl, A.S., Yield of Wafer Scale Interconnections, VLSI Systems Design, December, 1986, pp. 62–66.Google Scholar
  2. [2]
    Lathrop, J.W., Clark, R.S., Hull, J.E., and Jennings, R.M., A Discretionary Wiring System as the Interface between Design Automation and Semiconductor Array Manufacture, Proc. of the IEEE, Vol. 55 (1), Nov. 1967, pp. 1988–1997.CrossRefGoogle Scholar
  3. [3]
    Huang, G., Nunne, W., Spielberg, D., Mones, A., Fett, D., and Hampton, F., Silicon Packaging–A New Packaging Technique, Proc. Custom Int. Circ. Conf., Rochester, N.Y., May, 1983, pp. 142–146.Google Scholar
  4. [4]
    Johnson, R.R., The Significance of Wafer Scale Integration in Computer Design, Proc. of the IEEE Int. Conf. on Comp. Des., Oct. 1984, pp.Google Scholar
  5. [5]
    Donlan, Lt. B.J., McDonald, J.F., Taylor, G.F., Steinvorth, R.H., and Bergendahl A.S., Computer-Aided Design and Fabrication for Wafer Scale Integration, VLSI Design, April 1985, pp. 34–42.Google Scholar
  6. [6]
    Raffel, J.I., Anderson, A.H., Chapman, O.H., Konkle, K.H., Mathur, B., Soares, A.M., and Wyatt, P.W., A Wafer Scale Digital Integrator, Proc. of the I.E.E.E. Int. Conf. on Comp. Des., Oct. 1984, pp. 121–126.Google Scholar
  7. [7]
    McDonald, J.F., Greub, H.J., Steinvorth, R.H., Donlan, Capt B.J., and Bergendahl, A.S., Wafer Scale Interconnections for GaAs Packaging–Applications to RISC Architecture, IEEE Computer, April 1987, pp. 21–35.Google Scholar
  8. [8]
    Kung, H.T., Sproull, B., and Steele, G., Eds. VLSI Systems and Computations, Computer Science Press, Rockville, MD, 20850, pp 235–284.Google Scholar
  9. [9]
    Kailath, T., Modern Signal Processing, Hemisphere Publishing Corporation, New York, 1985.Google Scholar
  10. [10]
    Kung, S.Y., Whitehouse, H.J., and Kailath, T., Eds., VLSI and Modern Signal Processing, Prentice Hall, 1985.Google Scholar
  11. [11]
    Swartzlander, E.E., VLSI Signal Processing Systems, Kluwer Academic Publishers, Boston, 1986.Google Scholar
  12. [12]
    Cohen, R., McDonald, J.F., Sanya, M., and Woods, J.W., A Wafer Scale Integration Video Rate fully Recursive Two- Dimensional Filter, Proc. IEEE Conf. on Comp. Des., Oct. 1985, pp. 234–239.Google Scholar
  13. [13]
    Product Documentation, GaAs E/D LSI Programmable Cell Array - Preliminary TQ3000 Product Description, TriQuint Semiconductor, Inc., Tektronix Industrial Park, Group 700, P.O. Box 4935, Beaverton, OR, 97075.Google Scholar
  14. [14]
    Noll, T.G., Schmitt-Landsiedel, D., Klar, H., and Enders, G., A Pipelined 8×8 330 MHz NMOS Multiplier, IEEE J. Sol. State Ckts. (JSSC), Vol. SC-21(3), June 1986, pp. 411–416.Google Scholar
  15. [15]
    Bakoglu, H.B., Walker, J.T., and Meindl, J.D., A Symmetric Clock-Distribution Tree, and Optimized High-Speed Inter-connections for Reduced Clock Skew in ULSI and WSI Circuits, Proc. IEEE Conf. on Comp. Des., Oct. 1986, pp. 118–122.Google Scholar
  16. [16]
    Hornak, L.A., and Tewksbury, S.K., On the Feasibility of Through-Wafer Optical Interconnects for Hybrid Wafer-Scale Integrated Architectures, IEEE Trans. on Elec. Dev., Vol. ED-343(7), July 1987,pp. 1557–1563.Google Scholar
  17. [17]
    Grinberg, J., Nudd, G.R., Etchells, R.D., A Cellular VLSI Architecture, Computer, vol. 17, no. 1, pp. 69–81, Jan. 1984.CrossRefGoogle Scholar
  18. [18]
    McDonald, J.F., Stanton, M., Rajapakse, R. Lin H., Selvaraj, R., King, N., King, D., and Haslam, M., Adaptive Discretionary Wiring for Wafer Scale Integration using Electron Beam Lithography, Proc. SPIE, Vol 773 (Electron-Beam, X-Ray, and Ion-Beam Lithographies VI), P. D. Blais, Ed., Mar. 1987, pp. 140–149:Google Scholar
  19. [19]
    McDonald, J.F., Rajapakse, R.U., Lin, H.T., Selvaraj, R., Corelli, J.C., Jin, H.S., Balakrishnan,S., and Steckl, A.J., Optimized Focused Ion Beam Inspection and Repair of Wafer Scale Interconnections, Proc. SPIE, Vol 773, P. D. Blais, Ed., Mar. 1987, pp. 206–215.Google Scholar

Copyright information

© Plenum Press, New York 1988

Authors and Affiliations

  • H. Merchant
    • 1
  • H. Greub
    • 1
  • R. Philhower
    • 1
  • N. Majid
    • 1
  • J. F. McDonald
    • 1
  1. 1.Rensselaer Polytechnic InstituteTroyUSA

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