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VLSI Implementations of Neural Network Models

  • H. P. Graf
  • L. D. Jackel

Abstract

Three experimental CMOS VLSI circuits implementing connectionist neural network models are discussed in this paper. These chips contain networks of highly interconnected simple processing elements that execute a task distributed over the whole network. A combination of analog and digital computation allows us to build compact circuits so that large networks can be packed on a single chip. Such networks are well-suited for pattern matching and classification tasks, operations that are hard to solve efficiently on a serial architecture.

Keywords

Input Vector Neural Network Model Single Chip Inhibitory Connection Input Line 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Plenum Press, New York 1988

Authors and Affiliations

  • H. P. Graf
    • 1
  • L. D. Jackel
    • 1
  1. 1.AT&T Bell LaboratoriesHolmdelUSA

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