Abstract
In this paper, we present a new systolic algorithm to solve LU-decomposition effeciently in a 2-D systolic array. The LU-decomposition is the main step to solve a system of linear equations, a problem encountered in many scientific and industrial applications. Continuing growth of interest in systolic arrays poses new problems in ensuring the reliability of computations performed by such systems. A concurrent error detection scheme proposed earlier is applied to the new systolic LU-decomposition algorithm. The proposed concurrent error detection scheme requires small hardware overhead and no time overhead, since it utilizes the inherent idle cycles in the cells of the array.
The research reported has been supported in part by SDIO/IST contract No. N00014-87-K-0419 managed by U.S. Office of Naval Research.
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References
C.Mead and L. Conway, Introduction to VLSI systems, chapter 8, Addison-Wesley, 1980.
I. Koren, “A Reconfigurable and Fault-Tolerant VLSI Multiprocessor Array,” The 8th Symposium on Computer Architecture, IEEE and ACM, May 1981, pp. 425–442.
D.Gordon, I.Koren, and G.M.Silberman, “Restructuring hexagonal arrays of processors in the presence of faults,” to appear in J. VLSI Comput. Syst.
D.F.Barbe, “VHSIC Systems and Technology,” IEEE Computer, Feb. 1981, pp. 13–22.
Y.H.Choi, et al, “Fault Diagnosis of reconfigurable systolic arrays,” Intl Conf. Computer Design 84, pp. 451–455.
K.H.Huang and J.A.Abraham, “Low cost schemes for fault tolerant matrix operation with processor arrays”, FTCS-12, June 1982.
M.Sami and R.Stefanelli, “Reconfiguration Architectures for VLSI Processing Array,” Proc. of the IEEE, May 1986, pp. 712–722.
J.H.Kim and S.M.Reddy, “A Fault-Tolerant Systolic Array Design Using TMR Method, Int’l Conf. Computer Design 85,pp. 769–773.
C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley Pub. Co., Reading MA (1980), p. 282.
H.T.Kung, “Let’s design algorithms for VLSI systems,” Proc. Caltech. Conf. on VLSI, Jan. 1979, pp. 65–90.
R.K.Gulati and S.M.Reddy, “Concurrent Error Detection in VLSI Array Structures,” Int’l Conf.Computer Design 86, pp. 488–491.
S.J.Leon, “Linear Algebra with Application,” Macmillan Publishing Co., NY, 1980.
S.K Rao, private communication, Oct., 1987.
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© 1988 Plenum Press, New York
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Kim, J.H., Reddy, S.M. (1988). Fault-Tolerant LU-Decomposition in a Two-Dimensional Systolic Array. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds) Concurrent Computations. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-5511-3_29
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DOI: https://doi.org/10.1007/978-1-4684-5511-3_29
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