Fault-Tolerant Multistage Interconnection Networks for Multiprocessor Systems

  • V. P. Kumar
  • S. M. Reddy


In this paper we present a class of multipath multistage interconnection networks (MINs) called Augmented Shuffle-Exchange Networks. These MINs can be designed to have the degree of switch fault tolerance desired. They feature links among switches belonging to the same stage, and the number of links between adjacent stages is the same as in unique path MINs. The paths available from a source to a destination have varying lengths. Rerouting in the presence of faults or blocking can be accomplished in these MINs dynamically, without resorting to backtracking. In addition to tolerating faults in individual switches, the proposed networks make it possible to tolerate faults in groups of switches, thus facilitating on-line repair. Reliability and performance studies show that the proposed MINs achieve a significant improvement over unique path MINs and compare favorably with other multiple path MINs.


Output Link Switching Element Input Link Multistage Interconnection Network Multistage Network 
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  1. [1]
    V.E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic, Academic Press, New York, NY, 1965.Google Scholar
  2. [2]
    T.Y. Feng, “A Survey of Interconnection Networks,” Computer, Vol. 14, No. 12, December 1981, pp. 12–27.CrossRefGoogle Scholar
  3. [3]
    G.M Masson, G.C. Gingher, Shinji Nakamura, “A Sampler of Circuit Switching Networks,” Computer June 1979, pp. 32–48.Google Scholar
  4. [4]
    H.J. Siegel, “Interconnection Machines for SIMD Machines,” Computer June 1979, pp. 57–66.Google Scholar
  5. [5]
    L.R. Goke, G.J. Lipovski, “Banyan Networks for Partitioning Multiprocessor Systems,” Proc. 1st Annual Symposium on Computer Architecture, December 1971, pp. 21–28.Google Scholar
  6. [6]
    D.H. Lawrie, “Access and Alignment of Data in an Array Processor,” IEEE Trans. Comp., Vol. C-24, December 1975, pp. 1145–1155.Google Scholar
  7. [7]
    M.C. Pease, “The Indirect Binary n-Cube Microprocessor Array,” IEEE Trans. Comp., Vol. C-26, May 1977, pp. 458–473.Google Scholar
  8. [8]
    J.H. Patel, “Performance of Processor-Memory Interconnections for Multiprocessors,” IEEE Trans. Comp., October 1981, pp. 771–780.Google Scholar
  9. [9]
    C. Wu, T. Feng, “On a Class of Multistage Interconnection Networks,” IEEE Trans. Comp., Vol. C-29, August 1980, pp. 696–702.Google Scholar
  10. [10]
    K.E. Batcher, “The Flip Network in STARAN,” 1976 Intl. Conf. Parallel Processing, August 1976, pp. 65–71.Google Scholar
  11. [11]
    H.J. Siegel, R.J. McMillen, “The Multistage Cube: A Versatile Interconnection Network,” Computer, Vol. 14, No. 12, December 1981, pp. 65–76.CrossRefGoogle Scholar
  12. [12]
    G.H Barnes, S.F. Lundstrom, “Design and Validation of a Connection Network for Many-Processor Multiprocessor Systems,” Computer, December 1981, pp. 31–41Google Scholar
  13. [13]
    U.V. Premkumar, R. Kapur, M. Malek, G.J. Lipovski, and P. Horne, “Design and Implementation of the Banyan Interconnection Network in TRAC,” AFIPS 1980 Nat’l. Computer Conf., June 1980, pp. 643–653.Google Scholar
  14. [14]
    H.J. Siegel, L.J. Siegel, F.C. Kemmerer, P.T. Mueller,Jr., H.E. Smalley, Jr., and S.D. Smith, “PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition,” IEEE Trans. Computers, Vol. C-30, December 1981, pp. 934–947.Google Scholar
  15. [15]
    A. Gottlieb, R. Grishman, C.P. Kruskal, K.P. McAuliffe, L. Rudolph, and M. Snir, “The NYU Ultracomputer–Designing an MIMD Shared Memory Parallel Computer,” IEEE Trans. Computers, Vol. C-32, February 1983, pp. 175–189.Google Scholar
  16. [16]
    D. Gajski, D. Kuck, D. Lawrie and A. Sameh, “Cedar–A Large Scale Multiprocessor,” 1983 Intl. Conf. Parallel Processing, August 1983, pp. 524–529.Google Scholar
  17. [17]
    W. Crowther, J. Goodhue, E. Starr, R. Thomas, W. Milliken, T. Blackadar, “Performance Measurements on a 128-Node Butterfly Parallel Processor,” 1985 Intl. Conf. Parallel Processing, August 1985, pp. 531–540.Google Scholar
  18. [18]
    G.F. Pfister, W.C. Brantley, D.A. George, S.L. Harvey, W.J. Kleinfelder, K.P. McAuliffe, E.A. Melton, V.A. Norton and J. Weiss, “The IBM Research Parallel Processor Prototype (RP3): Introduction and Architecture,” 1985 Intl. Conf. Parallel Processing, August 1985, pp. 764–771.Google Scholar
  19. [19]
    K.M. Falavarjani and D.K. Pradhan, “A Design of Fault-Tolerant Interconnection Networks,” Unpublished Memo, 1981.Google Scholar
  20. [20]
    G.B. Adams, H.J. Siegel, “The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems,” IEEE Trans. Comp., Vol. 31, May 1982, pp. 443–454.CrossRefGoogle Scholar
  21. [21]
    D.M. Dias and J.R. Jump, “Augmented and Pruned N log N Multistage Networks,” 1982 Intl. Conf. Parallel Processing, August 1985, pp. 10–11.Google Scholar
  22. [22]
    R.J. McMillen, H.J. Siegel, “Routing Schemes for the Augmented Data Manipulator Network in an MIMD System,” IEEE Trans. Comp., Vol. C-31, December 1982, pp. 1202–1214.Google Scholar
  23. [23]
    H.J. Siegel, R. J. McMillen, “Dynamic Rerouting Tag Schemes for the Augmented Data Manipulator Network,” 8th Intl. Symp. on Computer Architecture, May 1981, pp 505–516.Google Scholar
  24. [24]
    R.J. McMillen, H.J. Siegel, “Performance and Fault-Tolerance Improvements in the Inverse Augmented Data Manipulator Network,” Proc. 9th Annual Symposium on Computer Architecture, April 1982, pp. 63–72.Google Scholar
  25. [25).
    D.S. Parker, C.S. Raghavendra, “The Gamma Network: A Multiprocessor Interconnection Network with Redundant Paths,” Proc. 9th Annual Symposium on Computer Architecture, June 1982, pp. 73–80.Google Scholar
  26. [26]
    C.S. Raghavendra, D.S. Parker, “Reliability Analysis of an Interconnection Network,” Proc. 4th International Conference on Distributed Computing Systems, May 1984, pp. 461–471.Google Scholar
  27. [27]
    L. Ciminiera, A. Serra, “A Fault-Tolerant Connecting Network for Multiprocessor Systems,” Proc. of the 1982 International Conference in Parallel Processing, August 1982, pp. 113–122.Google Scholar
  28. [28]
    K. Padmanabhan, D.H. Lawrie, “Fault-Tolerance Schemes in Shuffle-Exchange Type Interconnection Networks,” Proc. of the 1983 International Conference on Parallel Processing, August 1983, pp. 71–75.Google Scholar
  29. [29]
    K. Padmanabhan, D.H. Lawrie, “A Class of Redundant Path Multistage Interconnection Networks,” IEEE Trans. Comp., Vol. C-32, December 1983, pp. 1099–1108.Google Scholar
  30. [30]
    K. Padmanabhan, “Fault Tolerance and Performance Improvement in Multiprocessor Interconnection Networks,” Ph.D. Thesis, Dept. of Comp. Science, Univ. of Illinois, Urbana-Champaign, May 1984.Google Scholar
  31. [31]
    S.M. Reddy, V.P. Kumar, “On Fault-Tolerant Multistage Interconnection Networks,” Proc. of the 1984 International Conference of Parallel Processing, August 1984, pp. 155–164.Google Scholar
  32. [32]
    C.S. Raghavendra, A. Varma, “INDRA: A Class of Interconnection Networks with Redundant Paths,” 1984 Real Time Systems Symposium, December 1984.Google Scholar
  33. [33]
    V. Cherkassky, E. Opper, and M. Malek, “Reliability and Fault Diagnosis Analysis of Fault Tolerant Multistage Interconnection Networks,” 14th Intl. Symp. Fault-Tolerant Computing, June 1984, pp. 246–251.Google Scholar
  34. [34]
    V.P. Kumar and S.M. Reddy, “Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity,” 12th Intl. Symp. Computer Architecture, June 1985, pp. 376–386.Google Scholar
  35. [35]
    N. Tzeng, P. Yew, C. Zhu, “A Fault-Tolerant Scheme for Multistage Interconnection Networks,” 12th Intl. Symp. Computer Architecture, June 1985, pp. 368–375.Google Scholar
  36. [36]
    M. Jeng and H.J. Siegel, “A Fault-Tolerant Multistage Interconnection Network for Multiprocessor Systems Using Dynamic Redundancy,” 6th Intl. Conf. Distributed Computing Systems, May 1986, pp. 70–77.Google Scholar
  37. [37]
    G.B. Adams III and H.J. Siegel, “A Survey and Comparison of Fault-Tolerant Multistage Networks,” Computer, June 1987, pp. 14–27.Google Scholar
  38. [38]
    V.P. Kumar and S.M. Reddy, “Augmented Shuffle-Exchange Multistage Interconnection Networks,” Computer June 1987, pp. 30–40.Google Scholar
  39. [39]
    C.-T. A. Lea, “A Load-Sharing Banyan Network,” 1985 Intl. Conf. Parallel Processing, August 1985, pp. 317–324.Google Scholar
  40. [40]
    D.S. Wise, “Compact Layout of Banyan/FFT Networks,” Proc. CMU Conf. VLSI Systems and Computations, Computer Science Press (1981), pp. 186–195.Google Scholar
  41. [41]
    M.A. Franklin, “VLSI Performance Comparison of Banyan and Crossbar Communication Networks,” IEEE Trans. Computers, vol C-30, April 1981, pp. 283–290.Google Scholar
  42. [42]
    B.W. Arden and H. Lee, “Analysis of Chordal Ring Network,” IEEE Trans. Computers, Vol. C-30, April 1981, pp. 291–295.Google Scholar
  43. [43]
    L.N. Bhuyan, D.P. Agrawal, “Design and Performance of Generalized Interconnection Networks,” IEEE Trans. Comp., Vol. C-32, December 1983, pp. 1081–1090.Google Scholar
  44. [44]
    T.-y. Feng and C.-1. Wu, “Fault Diagnosis for a Class of Multistage Interconnection Networks,” IEEE Trans. Computers, Vol C-30, October 1981, pp. 743–758.Google Scholar
  45. [45]
    D.P. Agrawal, “Testing and Fault-Tolerance of Multistage Interconnection Networks,” Computer, April 1982, pp. 41–53.Google Scholar
  46. [46]
    W.K. Fuchs, J.A. Abraham, and K.-H. Huang, “Concurrent Error Detection in VLSI Interconnection Networks,” 10th Intl. Symp. Computer Architecture June 1983, pp. 309–315.Google Scholar
  47. [47]
    V.P. Kumar, On Highly Reliable, High Performance Multistage Interconnection Networks, Ph.D. Thesis, University of Iowa, December 1985.Google Scholar
  48. [48]
    K.S. Trivedi, Probability and Statistics with Reliability, Queueing and Computer Science Applications. Prentice-Hall, Englewood Cliffs, N.J., 1982.Google Scholar
  49. [49]
    A.M. Despain and D.A. Patterson, “X-Tree: A Tree-Structured Multiprocessor Computer Architecture,” 5th Ann. Symp. Computer Architecture, April 1978, pp. 144–151.Google Scholar
  50. [50]
    J.T. Blake, Comparative Analysis of Multistage Interconnection Networks, Ph.D. Thesis, Duke University, 1987.Google Scholar

Copyright information

© Plenum Press, New York 1988

Authors and Affiliations

  • V. P. Kumar
    • 1
  • S. M. Reddy
    • 2
  1. 1.AT&T Bell LaboratoriesHolmdelUSA
  2. 2.University of IowaIowa CityUSA

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