Abstract
The issue of self-testing and self-reconfiguration of two-dimensional VLSI array structures are discussed in this paper. Analysis and synthesis are facilitated by separating redundant circuits into two separate categories. ST-redundancy which represents built-in circuitry used solely for self-diagnosis, and SR-redundancy which represents extra resources used for fault-tolerance. The amount of redundancy can vary, e.g. a BIST method for self-testability employs approximately 10% ST-redundant circuitry while 200% of SR-redundancy plus a voter which is ST-redundant represents a signal-fault tolerant device. The concept is implemented as a double-layered VLSI array architecture. The developed model is very general. Some important arrangements like a centralized host system, a fault-tolerant distributed multiprocessor array developed by Kuhl and Reddy, or Koren’s self-reconfigurable VLSI array are special cases of S(M, N, t o ) systems, as introduced here. In one special case, 100% of ST-redundancy allows the testing to be performed at a polynomial time regardless of the array size.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
J. A. Abraham et. al., “Fault tolerance techniques for systolic arrays,” IEEE Computer, July 1987, pp. 65–74.
P. Agraval, “A novel fault tolerant distributed system architecture,” Proc. Int. Conf. Comp. Design: VLSI in Computers, ICCD 1985, pp. 760–763.
R. C. Aubusson, I. Catt, “Wafer scale integration: a fault-tolerant procedure,” IEEE Journal of Solid State Circuits, vol. SC-13, no. 3, June 1978, pp. 339–344.
M. A. Breuer, A. A. Ismael, “Roving emulation as a fault detection mechanism,” Proc. 13th Symp. Fault-tolerant Comput., June 1983, pp. 206–215.
M. G. Buehler, M. W. Sieviers, “Off-line, built-in test techniques for VLSI circuits,” IEEE Computer, June 1982, pp. 69–82.
Y. H. Choi, S. M. Han, M. M.lek, “Fault diagnosis of reconfigurable systolic arrays,” Proc. Int. Conf. Comp. Design: VLSI in Computers, ICCD 1984, pp. 451–455.
J. R. Dubin, Modern Algebra: An Introduction, John Wiley & Sons: New York, 1985.
D. S. Fussell and P. J. Varman, “Designing systolic algorithms for fault tolerance,” Proc. Int. Conf. Comp. Design, ICCD 1984, Oct. 1984, pp. 623–628.
N. S. Gollakota, F. G. Gray, “Reconfigurable cellular architecture,” Proc. 1984 Parallel Proc. Conf.,pp. 377–379.
J. W. Green, A. El Gamal, “Configuration of VLSI arrays in the presence of defects,” Journal of the ACM, vol. 31, no. 4, Oct. 1984, pp. 694–717.
J. H. Kim, S. M. Reddy, “A fault-tolerant systolic array design using TMR method,” Proc. Int. Conf. Comp. Design: VLSI in Computers, ICCD 1985, pp. 769–773.
I. Koren, “A reconfigurable and fault tolerant VLSI multiprocessor array,” Proc. 8th Symp. Comp. Architecture, 1981, pp. 425–442.
I. Koren and M. A. Breuer, “On the area and yield considerations for fault-tolerant VLSI processor arrays,” IEEE Trans. Comp., vol. C-33, Jan. 1984, pp. 21–27.
I. Koren and D. Pradhan, “Modeling the effect of redundancy on yield and performance of VLSI systems,” IEEE Trans. Comp., vol. C-36, March 1987, pp. 344–355.
J. Kuhl, S. Reddy, “Distributed fault-tolerance for large multiprocessor systems,” Proc. 7th Ann. Symp. Comp. Architecture, May 1980, pp. 23–30.
R. H. Kuhn, “Interstitial fault-tolerance - a technique for making systolic arrays fault-tolerant,” Proc. 16th Ann. Conf. Syst.,Jan. 1983, pp. 215224.
H. T. Kung, M. S. Lam, “Fault-tolerance and two-level pipelining in VLSI systolic arrays,” Proc. MIT Conf. Advanced Research in VLSI, Jan. 1984, pp. 76–83.
H. T. Kung, M. S. Lam, “Wafer scale integration and two level pipelined implementations of systolic arrays,” Journal of Parallel and Distributed Processing, vol. 1, no. 1, 1984.
F. T. Leighton, C. E. Leiseron, “Wafer scale integration of systolic arrays,” IEEE Trans. C.mp., vol. C-34, no. 5, May 1985, pp. 448–461.
T. E. Mangir and A. Avizienis, “Fault tolerant design for VLSI: effect of interconnect requirements on yield improvement of VLSI designs,” IEEE Trans. Comp., vol. C-31, No. 7, July 1982, pp. 609–615.
F. B. Manning, “An approach to highly integrated, computer maintained cellular array,” IEEE Trans. Comp.,vol. C-26, 1977, pp. 536552.
W. R. Moore, “A review of fault-tolerant techniques for the enhancement of integrated circuit yield,” Proc. IEEE, vol. 74, no. 5, May 1986, pp. 684–698.
D. K. Pradhan (ed.) Fault-Tolerant Computing, Theory and Techniques, Prentice Hall, Englewood Cliffs, NJ 1986.
A. L. Rosenberg, “The Diogenes approach to testable fault-tolerant arrays of processors,” IEEE Trans. Comp., vol. C-32, no. 10, Oct. 1983, pp. 902–909.
A. Rucinski, J. L. Pokoski, “A fault-tolerant distributed multiprocessor system for systolic algorithms,” Proc. Int. Conf. Comp. Design: VLSI in Computers, ICCD 85, Oct. 1985, pp. 754–759.
A. Rucinski, J. L. Pokoski, “Polystructural, reconfigurable, and fault-tolerant computers,” Int. Conf. Distr. Comp. Systems, May 1986, pp. 175–182.
A. Rucinski, J. L. Pokoski, “Distributed diagnostic reconfigurability in array structures,” 30th Midwest Symp. on Circuits and Systems, August 1987.
M. G. Sami and R. Stefanelli, “Reconfigurable architectures for VLSI implementation,” Proc. Nat’l Comp. Conf., NCC 1983, May 1983, pp. 565–577.
L. Snyder, “Introduction of the configurable, highly parallel computer,” IEEE Computer, Jan. 1982, pp. 47–56.
A. K. Somani, V. K. Agarwal, “System level diagnosis in systolic systems,” Proc. Int. Con! Comp. Design: VLSI in Computers, ICCD 1984, pp. 445–449.
A. Vergis, K. Steiglitz, “Testability conditions for bilateral arrays of combinational cells,” IEEE Trans. Comp., vol. C-35, no. 1, Jan. 1986, pp. 13–22.
S. M. Walters, F. G. Gray, R. A. Thompson. “Self-diagnosing cellular implementation of finite-state machines,” IEEE Trans. Comp., vol. C30, no. 12, Dec. 1981, pp. 953–959.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1988 Plenum Press, New York
About this chapter
Cite this chapter
Rucinski, A., Pokoski, J.L. (1988). Self-Diagnosable and Self-Reconfigurable VLSI Array Structures. In: Tewksbury, S.K., Dickinson, B.W., Schwartz, S.C. (eds) Concurrent Computations. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-5511-3_22
Download citation
DOI: https://doi.org/10.1007/978-1-4684-5511-3_22
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4684-5513-7
Online ISBN: 978-1-4684-5511-3
eBook Packages: Springer Book Archive