Self-Diagnosable and Self-Reconfigurable VLSI Array Structures

  • Andrzej Rucinski
  • John L. Pokoski


The issue of self-testing and self-reconfiguration of two-dimensional VLSI array structures are discussed in this paper. Analysis and synthesis are facilitated by separating redundant circuits into two separate categories. ST-redundancy which represents built-in circuitry used solely for self-diagnosis, and SR-redundancy which represents extra resources used for fault-tolerance. The amount of redundancy can vary, e.g. a BIST method for self-testability employs approximately 10% ST-redundant circuitry while 200% of SR-redundancy plus a voter which is ST-redundant represents a signal-fault tolerant device. The concept is implemented as a double-layered VLSI array architecture. The developed model is very general. Some important arrangements like a centralized host system, a fault-tolerant distributed multiprocessor array developed by Kuhl and Reddy, or Koren’s self-reconfigurable VLSI array are special cases of S(M, N, t o ) systems, as introduced here. In one special case, 100% of ST-redundancy allows the testing to be performed at a polynomial time regardless of the array size.


Systolic Array Multiprocessor System Array Structure Faulty Processor Systolic Algorithm 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Plenum Press, New York 1988

Authors and Affiliations

  • Andrzej Rucinski
    • 1
  • John L. Pokoski
    • 1
  1. 1.University of New HampshireDurhamUSA

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