The continuous advances in the semiconductor technologies involve smaller devices, faster circuits and increased circuit density, resulting in high performance large scale integrated (LSI) chips. The wiring between LSI chips requires a large number of high speed, high density interconnections. This paper describes the “Multilayer Ceramic (MLC)” process used in the IBM Corporation to fabricate multichip substrates with tight tolerances that meet these requirements by minimizing the interchip distances and providing multilayer wiring with dense vertical interconnection capability.
KeywordsBinder System Large Scale Integrate Metal Pattern Tight Tolerance Semiconductor Chip
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- 1.B. Schwartz and D.L. Wilcox, “Laminated Ceramics”, Proceedings of the Electronic Components Conference, IEEE, New York, 1967, pp. 17–26.Google Scholar
- 2.H.D. Kaiser, F.J. Pakulski, and A.F. Schmecken-becher, “A Fabrication Technique for Multilayer Ceramic Modules”, Solid State Technol. 15, No. 5, pp. 35–40 (May 1972).Google Scholar
- 3.A.J. Blodgett, “A Multilayer Ceramic Multi-Chip Module”, Proceedings of the Electronic Components Conference, IEEE, New York, 1980, pp. 283–285.Google Scholar
- 4.B.T. Clark and Y.M. Hill, “IBM Multichip Multi-layer Ceramic Modules for LSI Chips–Design for Performance and Density”, IEEE Trans. Components, Hybrids, Manuf. Technol. CHMT-3, pp. 89–93 (1980).Google Scholar
- 5.W.R. Swiss, “Fabricating Ceramic Sheets for Multi-layer Substrates”, Circuits Manufacturing, Vol. 19 No. 11, pp. 43–46 (1979).Google Scholar
- 9.W.D. Kingery, H.K. Bowen and D.R. Uhlmann, “Introduction to Ceramics”, Second Edition, 1976, John Wiley and Sons, New York.Google Scholar