Image Processing Unit Hardware Implementation
Conventional digital computers are inefficient for even simple local image processing operations in terms of cost-effectiveness. Image processing by serial computers requires a large amount of computing time. Programs and data are stored in the same memory and all operations are serially executed in the so-called “von Neuman” architecture, even though image processing could usually be performed mostly in parallel. Two-dimensional image data require a large amount of memory storage and usually exceed the main memory capacity. This results in much overhead time transferring image data between the main memory and secondary storage, e.g., magnetic disk. Therefore, we have elected to implement cost-effective image processing by developing special hardware optimized to overcome the above problems.
KeywordsFast Fourier Transform Host Computer Image Memory Vector Operation Output Address
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- Akers, A. E., Persoon, E., and Fu, K. S., “A Virtual Memory Computer for Image Processing,” Proc. IEEE Comp. Software Appl. Conf. (1977).Google Scholar
- Asada, H., Shinoda, H., Kidode, M., Yoneyama, T., Watanabe, S., and Mori, K., “Interactive Image Processing System with High Performance Special Processors,” Proc. 4th Internat’l Joint Conf. Pattern Recog., Kyoto (1978).Google Scholar
- Fu, K. S., “Special Computer Architectures for Pattern Recognition and Image Processing—An Overview,” Proc. Amer. Fed. Info. Proc. Soc. 47:1003–1013 (1978).Google Scholar
- Gold, B., and Rader, C. M., Digital Processing of Signals, New York, McGraw-Hill (1969).Google Scholar
- Hunt, B. R., “Computers and Images,” Proc. Soc. Photo. Ind. Engrs. 74:3–9 (1976).Google Scholar
- Mori, K., Kidode, M., Shinoda, H., and Asada, H., “Design of Local Parallel Pattern Processor for Image Processing,” Proc. Amer. Fed. Info. Proc. Soc. 47:1025–1031 (1978).Google Scholar