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A Multi-Microprocessor Architecture for Associative Processing of Image Data

  • H. Aiso
  • K. Sakamura
  • T. Ichikawa

Abstract

For the organization of image data retrieval systems, one of the most important features to be realized is a large scale semantic data base operating in a real-time environment. This calls for the development of a high-speed associative processor incorporating recent LSI technology. Therefore, we are developing a multi-microprocessor system designed to satisfy these requirements. This system, called “ARES,” was originally described by Ichikawa et al. (1977, 1978). ARES is essentially capable of associating stored data with a query item. Therefore, it is a problem-oriented computer designed for processing pattern or image data.

Keywords

Data Space Associative Processing Handwritten Character Cluster Control Data Word 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. Ichikawa, T., Sakamura, K., and Aiso, H., “ARES—A Memory, Capable of Associating Stored Information through Relevancy Estimation,” AFIPS Conf. Proc. 46:947–954 (1977).Google Scholar
  2. Ichikawa, T., Sakamura, K., and Aiso, H., “A Multi-microprocessor ARES with Associative Processing Capability on Semantic Data Bases,” AFIPS Conf. Proc. 47:1033–1039 (1978).Google Scholar

Copyright information

© Plenum Press, New York 1981

Authors and Affiliations

  • H. Aiso
    • 1
  • K. Sakamura
    • 1
  • T. Ichikawa
    • 1
    • 2
  1. 1.Department of Electrical EngineeringKeio UniversityKeioJapan
  2. 2.Research and Development LaboratoriesKokusai Denshin and Denwa Co., Ltd.Japan

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