Abstract
For experiments on future hadron colliders event rates of 108 / sec and data volumes of 1 Megabytes / recorded event are expected. The speed-up of several orders of magnitude in processing power over today’s on-line systems has to come mainly from progress in architectures. We have identified some representative triggering and data compaction algorithms, analyzed them as low level image processing tasks and have started to look into a few matching signal processing architectures that are commercially available. Fortunately we can benefit from the work of the very large international signal (image) processing and HDTV community and their commercial products. During the last decades they have solved many problems in the development of highly parallel signal (image) processing algorithms and architectures, e.g. systolic and/or wavefront array processors. The now (or in a predictable future) commercially available architectures seem to deliver the necessary computing power for future triggering and data compaction systems and will certainly have an important role to play in the design of such systems.
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References
S. Lone, R. K. Bock, Y. Ermolin, W. Krische, C. Ljuslin,. K. Zografos: Fine-grain parallel computer architectures in future triggers — NIM A288 (1990) pp. 507–516
R. Bock, W. Krische, S. Lone: Benchmarking computer architectures for HEP realtime algorithms.CERN-LAA/RT/88-08
M. Lea, ASP: A Cost-effective Parallel Microcomputer, IEEE Micro Oct 1988 F. Rohrbach,THE MPPC PROJECT,CERN/DRDC/90-76
The SPACAL Collaboration: Scintillating fibre calorimetry at the LHC — CERN/DRDC/P1, 1990
R. K. Bock, V. Buzuloi, W. Krischer: Algorithms and an image processing architecture for on-line electron identification from lateral profiles in SPACAL CERN LAA RT/90-01
DATACUBE: “MAXVIDEO User’s Manual”, Peabody,MA, 1988
A. K. Jain, P. M. Farrelle,V. R. Algazi: Image Data Compression in “Digital Image Processing Techniques ” (editor M. P. Ekstrom)-ACADEMIC PRESS 1984
G. Strang, Wavelets and dilation equations: A Brief Introduction SIAM Review. Vol.31, No.App. 614–627, December 1989
H. T. Kung, C. E. Leiserson: Systolic arrays for VLSI in Duff, Stewart (eds.): “Sparse Matrix Proceedings” 1979, SIAM 1979, pp. 256-282
H. T. Kung: Why systolic architectures? IEEE Computer.vol. 15. 1982, pp.37–46.
K. Bromley (editor): “Highly Parallel Signal Processing Architectures” SPIE Critical Review of Technology Series 19, vol. 614, 1986
K. Bromley, H. J. Whitehouse: Signal Processing Algorithms, Architectures and Implementations.SPIE: O-E/LASE 1986
S. Y. Kung: “VLSI Array Processors ”-Prentice Hall 1988
G. H. Golub, C. F. van Loan: “Matrix computations”, John Hopkins Press, Baltimore, 1989
W. M. Gentleman and H. T. Kung: Matrix triangularization by systolic arrays, Proc.SPIE Vol. 298 Real-Time Signal Processing IV (1981), pp. 19–26
J. G. McWhirter: Recursive Least Squares Minimisation using a systolic array Proc. SPIE. Vol. 431, Real-Time Signal Processing VI (1983), pp. 105–112
U. Schmidt, K. Caesar, T. Himmel: Data driven single chip video processor IEEE Transactions on Consumer Electronics 8/90
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© 1991 Plenum Press, New York
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Krischer, W. (1991). Image Processing at Supercolliders. In: Cifarelli, L., Ypsilantis, T. (eds) New Technologies for Supercolliders. Ettore Majorana International Science Series, vol 57. Springer, Boston, MA. https://doi.org/10.1007/978-1-4684-1360-1_25
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DOI: https://doi.org/10.1007/978-1-4684-1360-1_25
Publisher Name: Springer, Boston, MA
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