A Low-Cost Image Processing Facility Employing a New Hardware Realization of High-Speed Signal Processors

Abstract

In this paper, we describe a low-cost image-processing facility, assembled at the IBM Israel Scientific Center in Haifa, for computer aided processing of data obtained from medical ultrasonic imaging instruments. The system comprises of (1) an IBM Series/1 (S/1) minicomputer that serves as the overall system resources manager and programmer interface, (2) an experimental low cost high speed signal processor — the Simple Signal Processor (SSP) utilizing new reduced computational complexity (RCC) signal processing algorithms for convolution and discrete Fourier transform (DFT), (3) a Ramtek 9351 gray scale/pseudo color display, (4) a 20 MHz analog to digital converter, and (5) high speed microprocessor based interfaces between the SSP, the Ramtek, and the S/1 allowing burst block transfers between any pair.

First, the two main operational modes of the system are described highlighting the interaction between the various system components. The first mode is the realtime data acquisition mode in which the ultrasound RF signal is digitized and stored as a basic image. The second mode involves processing of the raw image data for purposes of enhancement, filtering, analysis, classification, compaction or similar functions, and display or storage of the resulting images.

Next, the architectural implications of the reduced computational complexity algorithms (e.g., the Winograd DFT), which require about one fifth the number of multiplications of previous known algorithms, are discussed briefly and the SSP is described in some detail. It is shown that the use of RCC algorithms enables the SSP, which is only a 4000-circuit processor, to provide throughput rates compatible with our real-time requirements, e.g., it does a 1008 complex point DFT in about 20 msec.

Finally, several image-processing examples are discussed, mainly convolution and spectral analysis, with emphasis on processing time analysis to identify the system bottlenecks. Based on these several guidelines for future system architecture for such a facility are included.