Abstract
The goal of this demonstrator of the ESPRIT project (824) was to prove the feasability of a high yield defect tolerant 16-bit microprocessor. Such a device is supposed to become the core of an application specific microprocessor-based system integrated on a single chip. A lot of effort was done to obtain a regular design allowing the introduction of standby elements at an adequate level. The area of redundant elements was limited to 30%.
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© 1989 Plenum Press, New York
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Leveugle, R., Soueidan, M., Wehn, N. (1989). Defect Tolerance in a 16-Bit Microprocessor. In: Koren, I. (eds) Defect and Fault Tolerance in VLSI Systems. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6799-8_17
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DOI: https://doi.org/10.1007/978-1-4615-6799-8_17
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