Abstract
This chapter deals with VHDL modeling style for modular specification and design reuse at the behavioral level. Modular specification allows to decompose a large design into smaller pieces which are easier to handle. Design reuse implies to be able to reuse existing components as black boxes during behavioral synthesis. These two concepts, when combined, are the basis of what is called structured design methodologies. These methods may be applied for both manual design and behavioral synthesis.
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© 1997 Springer Science+Business Media New York
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Jerraya, A.A., Ding, H., Kission, P., Rahmouni, M. (1997). Behavioral VHDL Description Styles for Design Reuse. In: Behavioral Synthesis and Component Reuse with VHDL. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-6315-0_4
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DOI: https://doi.org/10.1007/978-1-4615-6315-0_4
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-7899-0
Online ISBN: 978-1-4615-6315-0
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