Introduction

Abstract

Nowadays one of the major objectives within VLSI domain is the improvement of the design quality and of the designers’ productivity. This is due to the fact that the design process is characterized by 2 sets of factors: constant factors and variable ones. For instance typical large design budgets are usually fixed to around 10 to 15 persons over 18 months, and designers’ productivity has been evaluated to some 10 objects per day. Controversely, ASIC design complexity has been increasing exponentially since 1984 from a hundred thousand transistors, to reach 1 to 2 million transistors today. The design complexity forecast for the year 2000 is 7 million transistors for a 0.18 micron CMOS technology. It is expected that this exponential increase will continue until year 2010 in order to reach 40 million transistors [SIA94].