Analog Extensions to Verilog
Verilog-A is an analog hardware description language derived from Verilog. The mapping of Verilog-A behavioral descriptions to an underlying network equivalent model is discussed in detail. The chapter provides an overview of the capabilities of the Verilog-A language and presents examples of its features. The syntax and the special purpose built-in functions of Verilog-A are discussed. In addition issues relating to the interaction of the language with Spice type simulators are presented, for example language-simulator interaction in terms of timestep control and analysis dependent functions for noise and ac analysis are described. Finally multi-disciplinary modeling in Verilog-A is discussed.
KeywordsContribution Statement Source Type Transition Filter Potential Probe Flow Source
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