Analog Extensions to Verilog

  • Richard Trihy
Part of the Current Issues in Electronic Modeling book series (CIEM, volume 10)

Abstract

Verilog-A is an analog hardware description language derived from Verilog. The mapping of Verilog-A behavioral descriptions to an underlying network equivalent model is discussed in detail. The chapter provides an overview of the capabilities of the Verilog-A language and presents examples of its features. The syntax and the special purpose built-in functions of Verilog-A are discussed. In addition issues relating to the interaction of the language with Spice type simulators are presented, for example language-simulator interaction in terms of timestep control and analysis dependent functions for noise and ac analysis are described. Finally multi-disciplinary modeling in Verilog-A is discussed.

Keywords

Contribution Statement Source Type Transition Filter Potential Probe Flow Source 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    “Verilog-A Language Reference Manual 1.0,” Open Verilog International.Google Scholar
  2. [2]
    L.W. Nagel. SPICE2, “A computer program to simulate semiconductor circuits,” Technical Report Memo UCB/ERL M520, University of California Berkeley, May 1975.Google Scholar

Copyright information

© Springer Science+Business Media Dordrecht 1997

Authors and Affiliations

  • Richard Trihy
    • 1
  1. 1.Cadence Design SystemsSan JoseUSA

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